d5299f144f
Add --no-placer-timeout flag to override timeout during refinement
2022-12-19 22:58:52 -08:00
2712cbf6e4
Increase timeout
2022-12-19 14:00:19 -08:00
6e0311efca
Timeout when legal placement can't be found for cell
2022-12-17 16:07:57 -08:00
ccb573298c
heap: encourage more spreading of heterogenous chains
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-17 10:50:20 +00:00
603b60da8d
api: add explain_invalid option to isBelLocationValid
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:27:58 +01:00
d1afd6c0f1
heap: Remove custom bounding-box type
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:02:16 +01:00
e260ac33ab
refactor: ArcBounds -> BoundingBox
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:00:53 +01:00
c62a947a28
api: Make NetInfo* of checkPipAvailForNet const
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-02 14:20:39 +01:00
8a69bd0735
Fix "implicit copy constructor for 'Property' is deprecated"
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-11-10 10:57:41 +01:00
445d32497d
run clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-10-17 12:35:02 +02:00
9572f6f032
Modify code to meet the code style preferences
2022-09-24 14:46:35 +08:00
c702e15a3f
Add more sanity check for pointers
2022-09-24 12:03:44 +08:00
78f67ae5bc
fix runtime segmentation fault
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disable null pointer dereference!
2022-09-24 11:35:40 +08:00
f4e6bbd383
Merge pull request #1019 from antmicro/support-clock-relations
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Support cross-domain clock relations in timing analyser
2022-09-20 15:55:43 +02:00
9000c41c4b
Added the --ignore-rel-clk option to control timing checks for cross-domain paths, formatted code
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-09-20 14:40:40 +02:00
415c097df8
router2: Reserve source wire, too
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-09-20 13:42:51 +02:00
1f1bae3e23
Code cleanup
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-08-31 16:19:15 +02:00
60a6e8b070
Added timing check for cross-domain paths for related clocks
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-08-31 14:15:33 +02:00
9a61ad9234
Augmented TimingAnalyser class with detection of clock to clock relations
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-08-30 17:30:58 +02:00
a00b997cf1
add missing overrides
2022-08-22 12:35:24 +02:00
1aa797b820
Fix parameter order
2022-08-22 12:32:50 +02:00
05167fcb8b
pybindings: Mark CellInfo::bel as readonly
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bel bindings should be updated with bindBel/unbindBel during placement, or setting the BEL attribute for constraints before placement.
Fixes #522
Signed-off-by: gatecat <gatecat@ds0.me>
2022-08-18 15:09:41 +02:00
77c82b0fbf
refactor: id(stringf(...)) to new idf(...) helper
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-08-10 10:57:46 +01:00
09e388f453
netlist: Add PseudoCell API
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When implementing concepts such as partition pins or deliberately split
nets, there's a need for something that looks like a cell (starts/ends
routing with pins on nets, has timing data) but isn't mapped to a fixed
bel in the architecture, but instead can have pin mappings defined at
runtime.
The PseudoCell allows this by providing an alternate, virtual-function
based API for such cells. When a cell has `pseudo_cell` used, instead of
calling functions such as getBelPinWire, getBelLocation or getCellDelay
in the Arch API; such data is provided by the cell itself, fully
flexible at runtime regardless of arch, via methods on the PseudoCell
implementation.
2022-07-08 14:30:57 +02:00
e1ba379fb7
generic: Use arch_pybindings_shared
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-07-04 18:39:00 +02:00
447b5b905c
Don't assert on mixed domain paths in report
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-05-22 13:56:36 +01:00
1aa693732c
common: Correct a minor typo in the message
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-05-10 21:19:02 +10:00
19cade3b3b
prefine: Do full-tile swaps, too
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-19 18:37:16 +01:00
61b3e2e1ff
Move general parallel detail place code out of parallel_refine
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-17 20:10:49 +01:00
49f178ed94
Split up common into kernel,place,route
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-08 13:42:54 +01:00
774d3944b3
parallel_refine: Fix compile error with some configs
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-03-19 18:43:31 +00:00
e3b9c971f9
BUGFIX: disable the thousands separator
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The wire numbers are very large and it is undesirable to use a thousand
separator there. This is a side effect of enabling locale.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-16 15:05:27 +10:00
53ddbbaa85
Set the locale as early as possible
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-16 05:39:55 +10:00
df7e26c1aa
clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-03-09 17:12:59 +00:00
626eccdb89
Add missing part of commit aee35768.
2022-03-08 17:24:29 +00:00
aee35768f4
Disable parallel refinement on WebAssembly.
2022-03-05 16:32:44 +00:00
cc9f99a80c
parallel_refine: New, parallelised placement refinement pass
2022-03-03 18:37:53 +00:00
86699b42f6
Switch to potentially-sparse net users array
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This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-27 13:47:05 +00:00
434a9737bb
Add indexed_store container type
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-26 15:11:33 +00:00
75c45dbef1
Add IdStringList::concat overrides taking IdString
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-20 18:26:17 +00:00
6a32aca4ac
refactor: New member functions to replace design_utils
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-18 11:13:18 +00:00
30fd86ce69
refactor: New NetInfo and CellInfo constructors
2022-02-16 15:10:57 +00:00
84399caebe
run clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-03 15:28:46 +00:00
22e4081c73
gowin: Add GUI.
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* Items such as LUT, DFF, MUX, ALU, IOB are displayed;
* Local wires, 1-2-4-8 wires are displayed;
* The clock spines, taps and branches are displayed with some caveats.
For now, you can not create a project in the GUI because of possible
conflict with another PR (about GW1NR-9C support), but you can specify
the board in the command line and load .JSON and .CST in the GUI.
Although ALUs are displayed, but the CIN and COUT wires are not. This is
still an unsolved problem.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-01-29 14:45:17 +10:00
ae7c2261be
Switched integer pair hashing function from DJB2 to Cantor
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-01-11 15:28:13 +01:00
69a4e3e544
SSOArray: Implement move and assignment operators
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-30 21:32:24 +00:00
59874188a6
generic: Refactor for faster performance
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This won't affect Python-built arches significantly; but will be useful
for the future 'viaduct' functionality where generic routing graphs can
be built on the C++ side; too.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-30 11:54:08 +00:00
ddb084e9a8
archapi: Use arbitrary rather than actual placement in predictDelay
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This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.
A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-19 17:15:15 +00:00
f670de7b52
router1: Experimental timing-driven ripup support
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-18 20:58:44 +00:00
53ce8f3736
router1: Improve timing heuristic
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-18 14:30:48 +00:00
a120ae1fa7
python: Bind getBelLocation/getPipLocation
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-14 18:47:35 +00:00
0dafcc44ff
router2: Improve reservation debug logging
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-12 18:49:14 +00:00
c76e1be397
Merge pull request #867 from mkj/mkj/routerspeed2
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Improvements to ecp5 router speed
2021-12-12 15:37:36 +00:00
fc5b34254f
ecp5: Keep "visited" local
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Otherwise it keeps growing boundless and slows down small arcs
2021-12-12 22:09:11 +08:00
3c8af04ca5
router2: Error instead of hang in case of reservation conflicts
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-12 13:00:04 +00:00
b3edf81f6c
common: Improved the random seed initialisation for the context
2021-11-19 09:39:10 -05:00
8ad74edd66
router2: Disable criticality sorting towards end of routing
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-09 20:56:45 +01:00
b749ef5f56
hashlib: Support for std::array keys
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-07 17:05:16 +01:00
211b6b6b06
Fix Cygwin build
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-01 12:40:56 +01:00
1db3a87c62
Code formatting
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-29 14:59:09 +02:00
76f5874ffc
Brought back printout of critical path source file references, added clk-to-q, source and setup segment types
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-29 10:16:45 +02:00
1ed692aca9
Shifted moving of data containers after printing
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 18:01:30 +02:00
9018782eaa
Added a commandline option controlled writeout of per-net timing details
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
a9df3b425f
Added description of the JSON report structure.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
6deff56e83
Moved timing result report storage to the context, added its writeout to the current utilization and fmax report
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
c6dc1f535a
Added reporting critical paths in JSON format
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
d8571b6c00
Decoupled critical path report generation from its printing
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
12adbb81b1
Switched to JSON format for timing analysis report
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
99ae5ef38e
Added writing a CSV report with timing analysis of each net branch
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
0b0baf3446
idstring: Add 'in' function
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-27 19:18:40 +01:00
535b2490c4
Merge pull request #812 from antmicro/MacroCells
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Convert macros to clusters for better placement
2021-09-27 17:50:55 +01:00
ea489f6d93
Fix small isses and code formatting
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2021-09-27 16:16:33 +02:00
ab6990f908
router2: Allow overriding resource costs
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-24 19:11:37 +01:00
3cd459912a
Adding MacroCell placement
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2021-09-23 15:43:23 +02:00
fdcfe8cd81
Adding support for MacroCells
2021-09-23 15:43:23 +02:00
d9a71083e1
Merge pull request #825 from antmicro/chain_swap_fix
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Fix chain swap
2021-09-23 14:10:46 +01:00
8c97cbe341
Fix chain swap
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Issue was due to dest_bels being not cleared between clusters unbindes, causing
newly bind bels to be unbinded and having their old bel value changed to new bel value.
Then when swap failed 2 cells were being bind to a single bel.
I tested leaving dest_bels in the function scope and moving it to the loop scope.
Code with dest_bels in the loop scope was faster than leaving it in the function scope,
and checking if the cell is in the processed cluster.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2021-09-23 13:58:22 +02:00
562d02196c
python: Restore SIGINT handler while running a Python script
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-22 22:01:58 +01:00
4d90850676
placer1: Remove redundant relative constraint check
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Macros with potentially inconsistent spacing are now permissible.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-22 13:14:45 +01:00
e926cddca2
placer1: Fix cluster swap cost updates
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-18 11:11:24 +01:00
4730a4f339
timing: Always use max delay for required time
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-18 11:04:39 +01:00
287a860283
timing: Fix slack for unconstrained clocks
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-18 10:43:19 +01:00
f119f56e63
placer1: Allow swapping chains with other chains
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-17 21:51:18 +01:00
1e4f706ace
command: Allow running Python on failure for state introspection
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-16 20:56:32 +01:00
d08fb255a2
router2: Fix uninitialised values
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-06 13:29:23 +01:00
01b51fb715
router2: Fix explored count
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-02 17:08:54 +01:00
b85fe12234
python: Wrap PortRef by value
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-08-26 13:23:16 +01:00
de311e052f
python: Allow querying route delays
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-08-23 20:51:53 +01:00
df67783dd3
pybindings: Fix mapping for PortRefVector
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This is used by net.users for instance.
Removed by mistake in 4ac00af6faFixes #799
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-08-19 12:01:49 +02:00
f207068ee2
router2: Add experimental timing-driven ripup option
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-08-15 16:22:03 +01:00
42522c492c
router2: Alternative congestion cost schedule
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-08-15 16:22:03 +01:00
2a856db72c
router2: Adding some criticality heuristics
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-08-15 16:22:03 +01:00
64f6b8bc67
router2: Improved bidir routing and data structures
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-08-15 16:22:03 +01:00
ef1fbfc651
Merge pull request #787 from YosysHQ/gatecat/report
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Add JSON utilisation and timing report
2021-07-30 14:29:55 +01:00
b5a31d2e4e
router2: Mark dest as visited during backwards routing
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-30 09:14:46 +01:00
42f48b6dc0
router2: Improve debugability of pip conflicts
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-29 13:04:59 +01:00
d2007a386c
common: Add JSON timing and utilisation report
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-29 12:53:23 +01:00
4ac00af6fa
basectx: Add a field to store timing results
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-29 12:52:13 +01:00
504199e70e
nexus: Fix routeing of global clocks that also drive fabric
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-28 15:35:19 +01:00
ce92cdf8e4
router2: Update route delays even when routes are congested
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-28 12:15:36 +01:00
14c676ab49
timing: Allow overriding of route delays
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-28 11:20:28 +01:00
0e3b25468c
gui: Implement about dialog
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-25 12:06:51 +01:00
08bbe173ce
Fix definition of an empty IdStringList
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-20 15:51:04 +01:00
7abfeb11c3
interchange: xdc and place constr: address review comments
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-07-12 17:17:57 +02:00
d9668df818
interchange: add constraints constraints application routine
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-07-12 16:45:08 +02:00
76070a7647
timing: Fix out-of-bounds histogram bins in all cases
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-10 23:44:21 +01:00
5b2db015a9
Merge pull request #752 from YosysHQ/gatecat/du-mem-error
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design_utils: Fix memory error
2021-07-06 12:43:48 +01:00
3d0facf119
design_utils: Fix memory error
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-06 11:35:27 +01:00
31abefc8e4
interchange: Allow pseudo pip wires to overlap with bound site wires on the same net
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-06 10:38:08 +01:00
6fe071ad1d
router2: Dump pre-bound routes when routing fails in debug mode
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-06 10:21:31 +01:00
86bc708299
clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-01 13:18:34 +01:00
5c6b8a5f04
Preserve ArchArgs and reinit Context when applicable in GUI
2021-06-30 10:10:18 +02:00
889c295baf
sta: Fix a memory error introduced by the dict move
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-17 12:06:26 +01:00
ee65e6f32d
Merge pull request #724 from YosysHQ/gatecat/update-names
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Update deadnames and emails
2021-06-12 14:07:47 +01:00
2ffb081442
Fixing old emails and names in copyrights
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
f9d3b99e63
HeAP: Fix memory error introduced by switch to dict
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:07:11 +01:00
875004d300
gui: Don't destroy context when loading JSON
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-07 21:07:17 +01:00
dcbb322447
Remove redundant code after hashlib move
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
eca1a4cee4
Use hashlib in most remaining code
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
b8a68f5f35
Using hashlib in timing
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
ecc19c2c08
Using hashlib in arches
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
f4fed62c05
Use hashlib in routers
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:04:53 +01:00
43b8dde923
Use hashlib in placers
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:04:49 +01:00
579b98c596
Use hashlib for core netlist structures
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
ff72454f83
Add hash() member functions
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
76ef768864
common: Import hashlib from Yosys
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
315a5733d2
timing: Fix use of uninitialised value
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-01 11:40:55 +01:00
1595c07260
router2: Add heatmap by routing resource type
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-20 14:54:23 +01:00
5a41d2070c
Run clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-16 16:25:05 +01:00
3bb94192d5
mistral: Tidying up
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
f318898474
router2: Hacky workaround for slow Cyclone V convergence
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
511e46c40f
router2: Reduce verbosity when debugging
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
e5e2f7bc62
mistral: Add stub pack/place/route functions
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
b1d3eb07c3
archcheck: Use old connectivity check for CycloneV
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
5d1b8bf744
cyclonev: Add names and archcheck fixes
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
ee60e9c71c
router2: Add some boundness statistics
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-12 12:18:58 +01:00
e9fdbf618c
router2: Fix a typo
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-11 13:02:23 +01:00
b3b79122e1
command: Allow debug output for just placer or router
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-11 11:35:43 +01:00
65c611da02
router2: Reserve wires in more complex cases
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 21:20:09 +01:00
62613cb266
router2: Dynamicly expand bounding box based on congestion
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 19:04:24 +01:00
0d6be6f474
Add stub cluster API impl for remaining arches
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 13:12:52 +01:00
1bf202adcd
base_arch: Fix typo in getClusterPlacement
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 12:23:28 +01:00
14863bc04e
Update placers to use new cluster APIs
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 11:47:07 +01:00
6a3eacddd6
Add default base implementation of cluster API
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 11:47:06 +01:00
e1717bd771
Add BaseClusterInfo for base implementation
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 11:47:06 +01:00
b62dcc4bcc
arch_api: Outline of new cluster API
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 11:47:06 +01:00
f5c2547952
Update bits.h
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Fixed the variable name for windows MSVC builds.
2021-04-30 21:42:25 -05:00
dcb09ec8de
interchange: Implement getWireType
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-30 11:07:31 +01:00
6fbefb8f13
Merge pull request #681 from YosysHQ/gatecat/more-pybindings
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Add Python bindings for placement tests
2021-04-15 11:16:31 +01:00
d4aac6586c
Add Python bindings for placement tests
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-15 10:00:45 +01:00
d14db5c98f
Fix utilisation report when bel buckets are used
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-15 09:24:27 +01:00
4e346ecfba
Hash table refactoring
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-14 10:30:19 +01:00
ece10c3e04
timing: Fix domain init when loops are present
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-13 09:23:08 +01:00
5cd2a7f9c2
Merge pull request #674 from adamgreig/heap-spreader-fix
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HeAP: Skip high-strength cells in both cell loops
2021-04-12 14:16:22 +01:00
2fdf41ac01
HeAP: Skip high-strength cells in both cell loops.
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Previously only the first loop skipped cells with high belStrength,
but they can't be processed by the second loop either, so skip them
there too.
2021-04-12 13:42:20 +01:00
5b35329abb
fast_bels: Don't return pointer that might become invalid
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-12 10:23:41 +01:00
a519341112
Fix bug in router2 where router may give up too early.
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Was introduced in #612 . The logic before was intended to prevent the
router from terminating early when not using a bounding box, but the fix
in #612 simply removed that, meaning that the router might terminate
early incorrectly. The solution here is to only use the toexplore
hysteric once a solution is found.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:22:47 -07:00
8863b962fd
interchange: Fix illegal placements
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-30 15:28:19 +01:00
77bc2f9130
Add initial handling of local site inverters and constant signals.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:20:09 -07:00
8a50b02b9b
Use new parameter definition data in FPGA interchange processing.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-23 09:01:43 -07:00
e8d36bf5bd
Merge pull request #634 from litghost/add_get_bel_pin_type
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Add getBelPinType to Python interface.
2021-03-22 18:31:48 +00:00
4cd74bba2c
Add getBelPinType to Python interface.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:25:45 -07:00
e7d81913a4
Add "checkPipAvailForNet" to Arch API.
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This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:17:55 -07:00
2cd5bacca0
Refactor header structures in FPGA interchange Arch.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-19 21:36:06 -07:00
a3dd5b33bc
Run "make clangformat". to fix up master.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-18 13:30:37 -07:00
965ba00e0f
Moving hash map/set type selection to header.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-17 16:54:29 -07:00
e1cd98ba15
Add missing includes to fix WASI build.
2021-03-16 05:52:41 +00:00
351ca3b5ea
Use NEXTPNR_NAMESPACE macro's now that headers are seperated.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 18:49:12 +00:00
a8e35062c6
Merge pull request #621 from litghost/fix_header_nightmare
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Split nextpnr.h to allow for linear inclusion.
2021-03-15 17:00:52 +00:00
3c71911c26
opt-timing: Skip undriven nets
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-15 16:08:47 +00:00
fe4608386e
Split nextpnr.h to allow for linear inclusion.
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"nextpnr.h" is no longer the god header. Important improvements:
- Functions in log.h can be used without including
BaseCtx/Arch/Context. This means that log_X functions can be called
without included "nextpnr.h"
- NPNR_ASSERT can be used without including "nextpnr.h" by including
"nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in
any header file.
- Types defined in "archdefs.h" are now available without including
BaseCtx/Arch/Context. This means that utility classes that will be
used inside of BaseCtx/Arch/Context can be defined safely in a
self-contained header.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 09:05:23 -07:00
a342ae56e0
Add support for partially routed nets from the placer in router2.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-12 09:53:15 -08:00
7168cf8657
Add diagnostic prints to debug lookahead performance.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-10 09:12:50 -08:00
979e7b8709
Only depend on Abseil in threaded builds.
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Abseil has a hard dependency on threads (not just in the build system
but in many places in the base libraries), so there is no way to use
it on WASI at the moment.
2021-03-10 06:18:42 +00:00
d1f44fe91a
Merge pull request #607 from litghost/add_absl_flat_hash_map
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Add absl::flat_hash_map.
2021-03-09 08:48:25 +00:00
326b34887c
Merge pull request #609 from YosysHQ/gatecat/sta-v2
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Use new timing engine for criticality
2021-03-09 08:48:12 +00:00
da88d3d825
router2: Fix vast perf drop when leaving bounding box
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-08 15:06:30 +00:00
8a4bf3a780
timing: Integration tweaks
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 10:04:35 +00:00
98d1c5a411
timing: Skip route delays for unplaced/nullptr cells
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 11:34:20 +00:00
1ff2023f32
timing: Replace all users of criticality with new engine
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 11:29:11 +00:00
5f6aaa2475
timing: Use new engine in SA except for budget-based mode
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
ebc2527368
timing: Use new engine for HeAP
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
bbf5a7d461
timing: Add support for critical path printing
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
e681e0f14c
timing: Slack and criticality computation
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
296e6d10c2
timing: Produce plausible Fmax figure
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
541376f8cc
timing: Add Fmax printing for debugging
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
16e7bba87b
timing: Add backwards path walking
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
0528ceead1
timing: Add forward path walking
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
9c8d1bd6e3
timing: Compute domain pairs
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
534e69fbff
timing: Add port-domain tracking
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
7a546b1554
timing: Add topological sort from Yosys
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
d0772ce1e3
timing: Import cell delays to our own structures
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
fac6a6c068
timing: Data structures for STA rewrite
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
6e38e236f8
Merge pull request #604 from litghost/add_counter_test
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Add counter test for FPGA interchange
2021-03-03 07:06:07 +00:00
27fbee5233
Merge pull request #605 from litghost/add_placement_sanity_check
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Add placement sanity check in placer_heap.
2021-03-02 08:27:12 +00:00
392156c250
Correct spelling of RAII and add missing check in unlock_early.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-01 13:11:04 -08:00
0afa0da19f
Add absl::flat_hash_map.
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This lowers the CPU cost of using the flat wire map in router2, and should
use less memory as well.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-01 09:55:54 -08:00
99a2262d61
Use scope in router1/2 and placer1.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-01 09:43:39 -08:00
77a5a60a66
Fix latent bug with context locking in placer HeAP.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:40:58 -08:00
7878561970
Add placement sanity check in placer_heap.
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Also check return of placer1_refine.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:27:43 -08:00
Arjen Roodselaar
gatecat
airskywater
Maciej Kurc
Miodrag Milanovic
YRabbit
Catherine
Matt Johnston
dx-mon
Maciej Dudek
Sylvain Munaut
Alessandro Comodi
David Corrigan
Adam Greig
Keith Rothman