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4943 Commits

Author SHA1 Message Date
Lofty 4be8d4fa8d router2: improved partitioner 2025-08-09 05:06:26 +01:00
Lofty 5355222e09 Revert "gatemate: don't place cells all at once (#1528)" 
This reverts commit 2d393c2487.
 2025-08-09 04:35:20 +01:00
Lofty 2d393c2487
gatemate: don't place cells all at once (#1528) 2025-08-08 18:19:42 +02:00
Lofty 0ad43e6ec7
gatemate: remove placement density restriction (#1527) 2025-08-08 17:02:56 +02:00
YRabbit 0be6173064 Gowin. Add pin configurations bel/cell. 
Prior to the 5A series, pin functions (GPIO/SSPI/JTAG/DONE/etc) were
switched using fuses. This was done during the binary image formation
stage for loading into the FPGA using the command line keys of the
gowin_pack program.

The 5A series features certain ports that connect to VCC or GND
depending on whether the pin is used as SSPI or GPIO, for example. This
mechanism exists in parallel with fuses, but it is not described
anywhere, nor is there a corresponding primitive.

To generate working images, we have no choice but to simulate this thing
at the nextpnr stage, since VCC/GND routing is required.

For now, two flags are added, responsible for the SSPI and I2C pin
functions.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-08-08 13:27:37 +01:00
YRabbit 8ce9918405 Gowin. Remove search for old Apicula. 
This item is likely no longer necessary, as this executable file has
been unavailable since May, with the complete transition to Himbaechel.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-08-06 00:32:41 +01:00
Lofty 8938c73fc9
Merge pull request #1524 from YosysHQ/lofty/gatemate-mult-router 
gatemate: multiplier router
 2025-08-05 11:20:25 +01:00
Miodrag Milanovic 6b11a82d04 cleanup 2025-08-04 14:28:43 +02:00
Miodrag Milanovic f0e03ed6e7 cleanup 2025-08-04 14:23:18 +02:00
Miodrag Milanovic 89e7e059d8 cleanup 2025-08-04 13:55:19 +02:00
Miodrag Milanovic eb77362b97 Added logs under debug, and removed include for idstring.h 2025-08-04 13:50:19 +02:00
Miodrag Milanovic 88f52bcaba Fix multipliers on hardware 2025-08-04 13:26:26 +02:00
Lofty 60f3c25cb0 refactor inversion checker 2025-08-02 15:23:56 +01:00
Lofty fe7546fda5 Multiplier routing needs priority over clocks 2025-08-02 14:00:25 +01:00
Miodrag Milanovic 0810a9a243 More multiplier fixes 2025-08-02 13:04:13 +02:00
Miodrag Milanovic 6a3c4a2dca Enable pack_mult 2025-08-01 17:47:07 +02:00
Miodrag Milanovic 1748f38aad Add MULT_INVERT property 2025-08-01 17:46:48 +02:00
Lofty d26fc19724 clangformat 2025-08-01 16:46:22 +01:00
Miodrag Milanovic 49001df290 Fix when width is 1 2025-08-01 14:46:54 +02:00
Miodrag Milanovic da5d42dc9d Add missing connection 2025-08-01 12:25:22 +02:00
Lofty d53f774078 re-disable multiplier packing 2025-07-31 14:54:43 +01:00
Lofty 341e288488 fix swapped B inputs 2025-07-31 14:50:36 +01:00
Miodrag Milanovic 7d8b7da20b Add missing connection 2025-07-29 14:01:07 +02:00
Miodrag Milanović 7e68bea863
gatemate: fix SER_CLK wiring from CLKIN to PLL (#1523) 
* gatemate: fix SER_CLK wiring from CLKIN to PLL

* fix some output formatting

---------

Co-authored-by: Patrick Urban <patrick.urban@web.de>
 2025-07-29 11:26:49 +02:00
Lofty d26aa342b7 bugfix for x2y2 in8 binding a pip twice 2025-07-29 09:37:45 +01:00
Lofty ac8a12aee5 bugfix for number of hops 2025-07-29 09:37:45 +01:00
Lofty ff9fa6f4cc route comments 2025-07-29 09:37:45 +01:00
Lofty 95b32a2b56 working diagonal router; unhappy inversion checker 2025-07-29 09:37:45 +01:00
Lofty 9837b6f676 current progress (broken diagonal router) 2025-07-29 09:37:45 +01:00
Lofty 80664e55b7 current progress (fixed routing done?) 2025-07-29 09:37:45 +01:00
Lofty 78b614ed31 current progress 2025-07-29 09:37:45 +01:00
Lofty 1576703937 current progress (route zero driver too) 2025-07-29 09:37:45 +01:00
Lofty d1f80ca5bb current progress 2025-07-29 09:37:45 +01:00
Lofty 4cf33090a9 current progress 2025-07-29 09:37:45 +01:00
Lofty 8637e3bc18 heavy refactoring 2025-07-29 09:37:45 +01:00
Lofty 56e1452d31 refactor common routes 2025-07-29 09:37:45 +01:00
Lofty 90f5f719f3 current progress 2025-07-29 09:37:45 +01:00
Lofty 530a08606b current progress 2025-07-29 09:37:45 +01:00
Lofty 0829b46e9b move multiplier router to its own file 2025-07-29 09:37:45 +01:00
Lofty 0533a4c12b fixed missing pip 2025-07-29 09:37:45 +01:00
Hannah Ravensloft 8047369347 better inversion verification 2025-07-29 09:37:45 +01:00
Hannah Ravensloft f2c736ef81 Beginnings of the multiplier router 2025-07-29 09:37:45 +01:00
Miodrag Milanovic af6e9aa6a3 gatemate: Proper KEEPER handling 2025-07-28 12:11:32 +02:00
Miodrag Milanovic 2c20ca917c clangformat 2025-07-28 12:11:07 +02:00
YRabbit 356278d068
Gowin. Preparing to support the 5A series. (#1520) 
* Gowin. Preparing to support the 5A series.

Family recognition is added, as well as minor fixes, but base generation
itself is not allowed for GW5 - this gives the ability to test the next
Apicula release and still not break installations for those who simply
specify `HIMBAECHEL_GOWIN_DEVICES = "all"`.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Recognize GW5A family chips.

Construct chip base name for

 - GW5A-LV25MG121C1/l0 - TangPrimer 25k

 - GW5AT-LV60PG484A - TangMega 60k

 - GW5AST-LV138PG484A - TangMega 138k

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-07-23 08:45:24 +02:00
Miodrag Milanović 2d7d1e2408
gatemate: optimizations and cleanups (#1517) 
* Add log output

* Optimize CC_LUT1

* Update tests

* Optimize CC_LUT2 as well

* Use init enumerations

* Merge DFF in MX4

* Move repack code

* Move ramio code to pack_cpe

* Merge LUT1/2 to ADDF inputs

* Note actual CPE ports

* Merge DFF in ADDF

* Update FF params and ports first

* Check if DFFs are compatible before merging

* Optimize DFF/Latch

* Add reporting of optimized cells

* Optimize MX2/4

* Add statistics

* Use special nets for VCC/GND to skip using name

* Add warning for carry chain split

* Merge FFs where possible

* Cleanup

* Keep statistics out for now

* Add logs for packing sections

* review fixes

---------

Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2025-07-17 08:50:24 +02:00
YRabbit 4831e50843
Gowin. Allow clock network routing from GP pins. (#1518) 
Adds automatic connection of a general-purpose pin to the global clock
network.

The old behaviour, where such networks have to be explicitly specified,
can be activated with the command line key
"--vopt disable_gp_clock_routing".

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-07-13 09:24:40 +02:00
via 840354a28a
Fixes for I3C pins and RPLL (#1516) 2025-07-10 14:47:49 +02:00
myrtle 24785a3219
ecp5: Fix placement of ECLKSYNCB driving PLL CLKFB (#1512) 
* ecp5: Fix placement of ECLKSYNCB driving PLL CLKFB

Signed-off-by: gatecat <gatecat@ds0.me>

* ecp5: Improve PLL placement algorithm slightly

Signed-off-by: gatecat <gatecat@ds0.me>

---------

Signed-off-by: gatecat <gatecat@ds0.me>
 2025-07-08 08:50:12 +02:00
Miodrag Milanovic 0ebd7afab9 clangformat 2025-07-07 10:15:50 +02:00