Files
netgen/base
Tim Edwards c7fa0324d9 Added a piece of code that handles implicit pins in verilog by doing
the following:  (1) Checking that the parent cell is verilog,
(2) only running after the two cells themselves have been compared
and matched, then (3) added the missing pin or pins while reordering
pins on instances (note: this may not work if the verilog netlist is
the first passed to netgen;  that case needs to be checked).
2024-02-02 14:51:10 -05:00
..
2023-02-28 09:02:41 -05:00
2024-01-03 21:21:03 -05:00
2021-11-17 11:53:04 -05:00
2023-02-28 09:02:41 -05:00