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30 Commits
Author SHA1 Message Date
Tim Edwards 1be00bbd99 Merge branch 'master' into netgen-1.5 2020-03-27 03:00:21 -04:00
Tim Edwards 36aa373fb2 Corrected an error in the verilog read to correctly assign signals
to bus pins over an array of instances.  Takes care of the three
situations where the length of the signal bus equals the number of
instances;  where the length of the signal bus is a multiple of
the number of instances;  and where the number of instances is a
multiple of the length of the signal bus.
2020-03-26 11:53:52 -04:00
Tim Edwards 18f230fc46 Changed the default string size for tmpstr in flattenInstancesOf
from 200 to 1024.  Probably this should be dynamically allocated
and expanded as needed, as it is holding names that are of
increasing length as a hierarchy is descended and the instance
prefixes appended to the name.
2020-03-26 09:04:52 -04:00
Tim Edwards 03b241a5d4 Merge branch 'master' into netgen-1.5 2020-03-11 03:00:17 -04:00
Tim Edwards 0f5a618353 Corrected some problems with property matching in netcmp.c.
However, I have identified an issue that has not yet been resolved,
which is that there can be automorphisms that are potentially
broken by property matching.  Currently, the automorphisms are
arbitrarily resolved, then properties are matched---and may fail
accordingly.
2020-03-10 21:39:41 -04:00
Tim Edwards 43cebd1ef9 Merge branch 'master' into netgen-1.5 2020-03-06 03:00:39 -05:00
Tim Edwards 983c654086 Corrected error in property matching that can cause a segfault. 2020-03-05 15:20:46 -05:00
Tim Edwards 515fccc633 Corrected error in printing the name of a file when it is not found
in an "include" statement in either SPICE or verilog.  Modified pin
matching behavior to force cells in both netlists to be marked as
black-box entries if either one is marked as a black-box entry (this
may not be needed, but shouldn't do any harm, either).
2020-03-05 09:41:22 -05:00
Tim Edwards 0490959b07 Merge branch 'master' into netgen-1.5 2020-03-05 03:00:09 -05:00
Tim Edwards 7d94a7d5f6 Updated VERSION for new tarball. 2020-03-04 21:06:21 -05:00
Tim Edwards 39b3bb4d96 Changed behavior of MatchPins so that disconnected pins that are to
be removed because they do not match pins on the other cell being
compared, are marked with a different number (-2) than the usual
(-1).  CleanupPins then only removes those pins that are marked,
rather than all disconnected pins.
2020-03-04 21:01:43 -05:00
Tim Edwards 44673a04b6 Corrected the verilog parser to handle backslash-escape notation
in instance names, and to ignore bus delimiters inside backslash-
escaped names when determining if a net is a bus or not.
2020-03-04 16:55:53 -05:00
Tim Edwards a34f08b20a Corrected problem in flattening code that would attempt to flatten
a cell that mismatched by having zero instances.  Which fails and
repeats indefinitely.
2020-03-04 15:17:42 -05:00
Tim Edwards 240a276431 Changed behavior of "equate pins" to detect placeholder cells as
a different way of treating "black box" cells.  Even when the
"-blackbox" option is specified, any cell that has no definition
will be treated as a black box.  This allows comparison of a
black-box netlist against a non-black-box netlist, such as a
verilog netlist vs. a SPICE netlist, without forcing the black-box
attribute on the SPICE netlist.  Then, if the SPICE netlist
contains cells without elements such as fill/decap/tap cells,
they can be flattened and removed instead of forcing an error or
requiring the use of "ignore".
2020-03-03 10:50:45 -05:00
Tim Edwards dc841f3293 Merge branch 'master' into netgen-1.5 2020-02-24 17:35:04 -05:00
Tim Edwards f7037fc9e6 Updated VERSION manually; checking regeneration of tarball. 2020-02-24 17:34:38 -05:00
Tim Edwards 23fb9356f4 Corrected Makefile to use -include instead of include on defs.mak
so that "make distclean" works.
2020-02-24 17:31:06 -05:00
Tim Edwards 05bcfede69 Merge branch 'master' into netgen-1.5 2020-02-24 16:39:19 -05:00
Tim Edwards 027b4ae468 Test update of VERSION. 2020-02-24 16:38:56 -05:00
Tim Edwards 72ed78e55a Update for change in ocd git script 2020-02-24 15:04:59 -05:00
Tim Edwards 59bb8a89c0 "ocd_git_pure automatic update to repo" 2020-02-24 15:04:27 -05:00
Tim Edwards 08a442fda2 Removed VERSION from .gitignore, and updated VERSION. 2020-02-24 11:50:38 -05:00
Tim Edwards 9bdaee652e "ocd_git_pure automatic update to repo" 2020-02-18 03:00:14 -05:00
Tim Edwards 9879b58f83 Merge branch 'master' into netgen-1.5 2020-02-18 03:00:13 -05:00
Tim Edwards cc0cc512c0 Modified the Makefile per the patch from Charlene at OpenBSD to
add GR_LIBS to the list of options to CC, as this apparently
prevents problems with older binutils, and should not affect
builds otherwise.
2020-02-17 14:04:40 -05:00
Tim Edwards 9e3b705fcc "ocd_git_pure automatic update to repo" 2020-02-11 03:00:09 -05:00
Tim Edwards d2c9129242 Merge branch 'master' into netgen-1.5 2020-02-11 03:00:09 -05:00
Tim Edwards e9c0596dfe One additional change to allow a single value to the "format" command
to apply to both column widths.
2020-02-10 09:17:45 -05:00
Tim Edwards 9a1e295367 Based on code from John Wood, added command "netgen::format <col1_width>
<col2_width>" to set the output format width, to avoid the fixed column
widths of 41 characters which can truncate long strings in the output
such as deep cell hierarchies.  This command can be placed in the setup
script to widen the output columns to accomodate the result (to-do:
provide an "auto" mode to automatically determine the best width).
2020-02-10 09:11:34 -05:00
Tim Edwards 942f421fa3 "ocd_git_pure automatic update to repo" 2020-01-30 03:01:39 -05:00
11 changed files with 369 additions and 172 deletions
+1 -1
View File
@@ -9,7 +9,7 @@ MODULES = base
MAKEFLAGS =
INSTALL_CAD_DIRS = lib doc
include defs.mak
-include defs.mak
all: $(ALL_TARGET)
+1 -1
View File
@@ -1 +1 @@
1.5.135
1.5.145
+6 -6
View File
@@ -259,7 +259,7 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
struct nlist *ChildCell;
struct objlist *tmp, *ob2, *ob3;
int notdone, rnodenum;
char tmpstr[200];
char tmpstr[1024];
int nextnode, oldmax, numflat = 0;
#if !OLDPREFIX
int prefixlength;
@@ -1166,7 +1166,7 @@ struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
while (ob && obt && (ob->type > FIRSTPIN || ob == firstpin) &&
ob->model.class != NULL) {
nob = ob->next;
if ((obt->type == PORT) && (obt->node == -1)) {
if ((obt->type == PORT) && (obt->node == -2)) {
/* Remove this pin */
@@ -1238,7 +1238,7 @@ int CleanupPins(char *name, int filenum)
for (ob = ThisCell->cell; ob != NULL; ob = ob->next) {
if (ob->type != PORT) break;
if (ob->node == -1) {
if (ob->node == -2) {
needscleanup = 1;
break;
}
@@ -1265,7 +1265,7 @@ int CleanupPins(char *name, int filenum)
}
else if (ob->type != PORT) break;
nob = ob->next;
if (ob->node == -1) {
if (ob->node == -2) {
if (lob == NULL) {
ThisCell->cell = ob->next;
}
@@ -1539,7 +1539,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
/* (it without regard to cell1) improves the matching. */
else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell2 != NULL) &&
(ecomp->cell2->class == CLASS_SUBCKT)) {
(ecomp->num2 != 0) && (ecomp->cell2->class == CLASS_SUBCKT)) {
ecomp->add2 = -ecomp->num2;
match = 1;
for (ob2 = ecomp->cell2->cell; ob2; ob2 = ob2->next) {
@@ -1597,7 +1597,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
/* (it without regard to cell1) improves the matching. */
else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
(ecomp->cell1->class == CLASS_SUBCKT)) {
(ecomp->num1 != 0) && (ecomp->cell1->class == CLASS_SUBCKT)) {
ecomp->add1 = -ecomp->num1;
match = 1;
for (ob2 = ecomp->cell1->cell; ob2; ob2 = ob2->next) {
+216 -141
View File
@@ -151,6 +151,10 @@ static struct NodeList *NodeListFreeList = NULL;
struct nlist *Circuit1;
struct nlist *Circuit2;
/* global variables to handle the output line width */
int left_col_end = 43;
int right_col_end = 87;
/* if TRUE, always partition ALL classes */
int ExhaustiveSubdivision = 0;
@@ -1147,12 +1151,16 @@ void FormatIllegalElementClasses()
struct FormattedList **elist1, **elist2;
struct ElementClass *escan;
int found, numlists1, numlists2, n1, n2, n, f1, f2, i, maxf;
char ostr[89];
char *ostr;
char *estr;
char permname[80];
char permcount[80];
char *permname;
char *permcount;
int bytesleft;
ostr = CALLOC(right_col_end + 2, sizeof(char));
permname = CALLOC(right_col_end + 2, sizeof(char));
permcount = CALLOC(right_col_end + 2, sizeof(char));
found = 0;
for (escan = ElementClasses; escan != NULL; escan = escan->next)
if (!(escan->legalpartition)) {
@@ -1164,14 +1172,14 @@ void FormatIllegalElementClasses()
/* Print in side-by-side format */
*(ostr + 43) = '|';
*(ostr + 87) = '\n';
*(ostr + 88) = '\0';
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
snprintf(ostr, 43, "Circuit 1: %s", Circuit1->name);
snprintf(ostr + 44, 43, "Circuit 2: %s", Circuit2->name);
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
*(ostr + left_col_end) = '|';
*(ostr + right_col_end) = '\n';
*(ostr + right_col_end + 1) = '\0';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
snprintf(ostr, left_col_end, "Circuit 1: %s", Circuit1->name);
snprintf(ostr + left_col_end + 1, left_col_end, "Circuit 2: %s", Circuit2->name);
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
}
found = 1;
@@ -1196,6 +1204,9 @@ void FormatIllegalElementClasses()
if (check_interrupt()) {
FreeFormattedLists(elist1, n1);
FreeFormattedLists(elist2, n2);
FREE(ostr);
FREE(permname);
FREE(permcount);
return;
}
#endif
@@ -1212,31 +1223,31 @@ void FormatIllegalElementClasses()
for (n = 0; n < ((n1 > n2) ? n1 : n2); n++) {
if (n != 0) {
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
Fprintf(stdout, ostr);
} else {
for (i = 0; i < 87; i++) *(ostr + i) = '-';
for (i = 0; i < right_col_end; i++) *(ostr + i) = '-';
Fprintf(stdout, ostr);
*(ostr + 43) = '|';
*(ostr + left_col_end) = '|';
}
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
if (n < n1) {
estr = elist1[n]->name;
if (*estr == '/') estr++; // Remove leading slash, if any
snprintf(ostr, 43, "Instance: %s", estr);
snprintf(ostr, left_col_end, "Instance: %s", estr);
}
else
snprintf(ostr, 43, "(no matching instance)");
snprintf(ostr, left_col_end, "(no matching instance)");
if (n < n2) {
estr = elist2[n]->name;
if (*estr == '/') estr++; // Remove leading slash, if any
snprintf(ostr + 44, 43, "Instance: %s", estr);
snprintf(ostr + left_col_end + 1, left_col_end, "Instance: %s", estr);
}
else
snprintf(ostr + 44, 43, "(no matching instance)");
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
snprintf(ostr + left_col_end + 1, left_col_end, "(no matching instance)");
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
if (n >= n1)
@@ -1249,12 +1260,12 @@ void FormatIllegalElementClasses()
f1 = f2 = 0;
while ((f1 < maxf) || (f2 < maxf)) {
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
if (n < n1) {
if (f1 < elist1[n]->fanout) {
if (elist1[n]->flist[f1].permute == (char)1) {
snprintf(ostr, 43, " %s = %d", elist1[n]->flist[f1].name,
snprintf(ostr, left_col_end, " %s = %d", elist1[n]->flist[f1].name,
elist1[n]->flist[f1].count);
}
else {
@@ -1276,7 +1287,7 @@ void FormatIllegalElementClasses()
sprintf(value, "%d", elist1[n]->flist[f1].count);
strcat(permcount, value);
strcat(permcount, ")");
snprintf(ostr, 43, " %s = %s", permname, permcount);
snprintf(ostr, left_col_end, " %s = %s", permname, permcount);
}
}
}
@@ -1284,7 +1295,7 @@ void FormatIllegalElementClasses()
if (n < n2) {
if (f2 < elist2[n]->fanout) {
if (elist2[n]->flist[f2].permute == (char)1) {
snprintf(ostr + 44, 43, " %s = %d", elist2[n]->flist[f2].name,
snprintf(ostr + left_col_end + 1, left_col_end, " %s = %d", elist2[n]->flist[f2].name,
elist2[n]->flist[f2].count);
}
else {
@@ -1306,22 +1317,26 @@ void FormatIllegalElementClasses()
sprintf(value, "%d", elist2[n]->flist[f2].count);
strcat(permcount, value);
strcat(permcount, ")");
snprintf(ostr + 44, 43, " %s = %s", permname, permcount);
snprintf(ostr + left_col_end + 1, left_col_end, " %s = %s", permname, permcount);
}
}
}
f2++;
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
}
}
FreeFormattedLists(elist1, numlists1);
FreeFormattedLists(elist2, numlists2);
for (i = 0; i < 87; i++) *(ostr + i) = '-';
for (i = 0; i < right_col_end; i++) *(ostr + i) = '-';
Fprintf(stdout, ostr);
*(ostr + 43) = '|';
*(ostr + left_col_end) = '|';
}
FREE(ostr);
FREE(permname);
FREE(permcount);
}
/*
@@ -1502,8 +1517,9 @@ void FormatIllegalNodeClasses()
struct FormattedList **nlists1, **nlists2;
struct NodeClass *nscan;
int found, numlists1, numlists2, n1, n2, n, f, i, maxf;
char ostr[89];
char *ostr;
ostr = CALLOC(right_col_end + 2, sizeof(char));
found = 0;
for (nscan = NodeClasses; nscan != NULL; nscan = nscan->next)
@@ -1515,14 +1531,14 @@ void FormatIllegalNodeClasses()
Fprintf(stdout, "Class fragments follow (with fanout counts):\n");
/* Print in side-by-side format */
*(ostr + 43) = '|';
*(ostr + 87) = '\n';
*(ostr + 88) = '\0';
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
snprintf(ostr, 43, "Circuit 1: %s", Circuit1->name);
snprintf(ostr + 44, 43, "Circuit 2: %s", Circuit2->name);
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
*(ostr + left_col_end) = '|';
*(ostr + right_col_end) = '\n';
*(ostr + right_col_end + 1) = '\0';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
snprintf(ostr, left_col_end, "Circuit 1: %s", Circuit1->name);
snprintf(ostr + left_col_end + 1, left_col_end, "Circuit 2: %s", Circuit2->name);
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
}
found = 1;
@@ -1545,6 +1561,7 @@ void FormatIllegalNodeClasses()
if (check_interrupt()) {
FreeFormattedLists(nlists1, n1);
FreeFormattedLists(nlists2, n2);
FREE(ostr);
return;
}
#endif
@@ -1561,25 +1578,25 @@ void FormatIllegalNodeClasses()
for (n = 0; n < ((n1 > n2) ? n1 : n2); n++) {
if (n != 0) {
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
Fprintf(stdout, ostr);
} else {
for (i = 0; i < 87; i++) *(ostr + i) = '-';
for (i = 0; i < right_col_end; i++) *(ostr + i) = '-';
Fprintf(stdout, ostr);
*(ostr + 43) = '|';
*(ostr + left_col_end) = '|';
}
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
if (n < n1)
snprintf(ostr, 43, "Net: %s", nlists1[n]->name);
snprintf(ostr, left_col_end, "Net: %s", nlists1[n]->name);
else
snprintf(ostr, 43, "(no matching net)");
snprintf(ostr, left_col_end, "(no matching net)");
if (n < n2)
snprintf(ostr + 44, 43, "Net: %s", nlists2[n]->name);
snprintf(ostr + left_col_end + 1, left_col_end, "Net: %s", nlists2[n]->name);
else
snprintf(ostr + 44, 43, "(no matching net)");
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
snprintf(ostr + left_col_end + 1, left_col_end, "(no matching net)");
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
if (n >= n1)
@@ -1591,17 +1608,17 @@ void FormatIllegalNodeClasses()
nlists1[n]->fanout : nlists2[n]->fanout;
for (f = 0; f < maxf; f++) {
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
if (n < n1)
if (f < nlists1[n]->fanout) {
if (nlists1[n]->flist[f].permute <= 1)
snprintf(ostr, 43, " %s/%s = %d",
snprintf(ostr, left_col_end, " %s/%s = %d",
nlists1[n]->flist[f].model,
nlists1[n]->flist[f].name,
nlists1[n]->flist[f].count);
else {
snprintf(ostr, 43, " %s/(%s) = %d",
snprintf(ostr, left_col_end, " %s/(%s) = %d",
nlists1[n]->flist[f].model,
nlists1[n]->flist[f].name,
nlists1[n]->flist[f].count);
@@ -1611,29 +1628,30 @@ void FormatIllegalNodeClasses()
if (n < n2)
if (f < nlists2[n]->fanout) {
if (nlists2[n]->flist[f].permute <= 1)
snprintf(ostr + 44, 43, " %s/%s = %d",
snprintf(ostr + left_col_end + 1, left_col_end, " %s/%s = %d",
nlists2[n]->flist[f].model,
nlists2[n]->flist[f].name,
nlists2[n]->flist[f].count);
else {
snprintf(ostr + 44, 43, " %s/(%s) = %d",
snprintf(ostr + left_col_end + 1, left_col_end, " %s/(%s) = %d",
nlists2[n]->flist[f].model,
nlists2[n]->flist[f].name,
nlists2[n]->flist[f].count);
FREE(nlists2[n]->flist[f].name);
}
}
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
}
}
FreeFormattedLists(nlists1, numlists1);
FreeFormattedLists(nlists2, numlists2);
for (i = 0; i < 87; i++) *(ostr + i) = '-';
for (i = 0; i < right_col_end; i++) *(ostr + i) = '-';
Fprintf(stdout, ostr);
*(ostr + 43) = '|';
*(ostr + left_col_end) = '|';
}
FREE(ostr);
}
/*
@@ -2770,26 +2788,28 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
struct NodeList *n;
struct nlist *tp1, *tp2, *tp;
int C1, C2, i;
char ostr[89];
char *ostr;
int needflat = 0;
#ifdef TCL_NETGEN
Tcl_Obj *clist1, *clist2;
#endif
ostr = CALLOC(right_col_end + 2, sizeof(char));
if (Debug == 0) {
Fprintf(stdout, "\nSubcircuit summary:\n");
*(ostr + 43) = '|';
*(ostr + 87) = '\n';
*(ostr + 88) = '\0';
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
*(ostr + left_col_end) = '|';
*(ostr + right_col_end) = '\n';
*(ostr + right_col_end + 1) = '\0';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
snprintf(ostr, 43, "Circuit 1: %s", Circuit1->name);
snprintf(ostr + 44, 43, "Circuit 2: %s", Circuit2->name);
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
snprintf(ostr, left_col_end, "Circuit 1: %s", Circuit1->name);
snprintf(ostr + left_col_end + 1, left_col_end, "Circuit 2: %s", Circuit2->name);
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
for (i = 0; i < 43; i++) *(ostr + i) = '-';
for (i = 44; i < 87; i++) *(ostr + i) = '-';
for (i = 0; i < left_col_end; i++) *(ostr + i) = '-';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = '-';
Fprintf(stdout, ostr);
}
@@ -2841,16 +2861,16 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
if (Debug == 0) {
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
snprintf(ostr, 43, "%s (%d)", Esrch->object->model.class, C1);
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
snprintf(ostr, left_col_end, "%s (%d)", Esrch->object->model.class, C1);
if (C2 > 0)
snprintf(ostr + 44, 43, "%s (%d)%s", tp2->name, C2,
snprintf(ostr + left_col_end + 1, left_col_end, "%s (%d)%s", tp2->name, C2,
(C2 == C1) ? "" : " **Mismatch**");
else {
snprintf(ostr + 44, 43, "(no matching element)");
snprintf(ostr + left_col_end + 1, left_col_end, "(no matching element)");
}
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
}
#ifdef TCL_NETGEN
@@ -2908,11 +2928,11 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
}
if (Debug == 0) {
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
snprintf(ostr, 43, "(no matching element)");
snprintf(ostr + 44, 43, "%s (%d)", Esrch->object->model.class, C2);
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
snprintf(ostr, left_col_end, "(no matching element)");
snprintf(ostr + left_col_end + 1, left_col_end, "%s (%d)", Esrch->object->model.class, C2);
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
}
#ifdef TCL_NETGEN
@@ -2957,13 +2977,13 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
C1, C2);
}
else {
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
snprintf(ostr, 43, "Number of devices: %d%s", C1, (C1 == C2) ? "" :
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
snprintf(ostr, left_col_end, "Number of devices: %d%s", C1, (C1 == C2) ? "" :
" **Mismatch**");
snprintf(ostr + 44, 43, "Number of devices: %d%s", C2, (C1 == C2) ? "" :
snprintf(ostr + left_col_end + 1, left_col_end, "Number of devices: %d%s", C2, (C1 == C2) ? "" :
" **Mismatch**");
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
}
@@ -2983,6 +3003,7 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
}
#endif
FREE(ostr);
return 0;
}
@@ -3006,24 +3027,28 @@ void FirstNodePass(struct Node *N, int dolist)
Fprintf(stderr, "Net Mismatch: Circuit 1 has %d, Circuit 2 has %d.\n",C1,C2);
}
else {
char ostr[89];
char *ostr;
int i;
*(ostr + 43) = '|';
*(ostr + 87) = '\n';
*(ostr + 88) = '\0';
ostr = CALLOC(right_col_end + 2, sizeof(char));
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
snprintf(ostr, 43, "Number of nets: %d%s", C1, (C1 == C2) ? "" :
*(ostr + left_col_end) = '|';
*(ostr + right_col_end) = '\n';
*(ostr + right_col_end + 1) = '\0';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
snprintf(ostr, left_col_end, "Number of nets: %d%s", C1, (C1 == C2) ? "" :
" **Mismatch**");
snprintf(ostr + 44, 43, "Number of nets: %d%s", C2, (C1 == C2) ? "" :
snprintf(ostr + left_col_end + 1, left_col_end, "Number of nets: %d%s", C2, (C1 == C2) ? "" :
" **Mismatch**");
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
for (i = 0; i < 87; i++) *(ostr + i) = '-';
for (i = 0; i < right_col_end; i++) *(ostr + i) = '-';
Fprintf(stdout, ostr);
FREE(ostr);
}
#ifdef TCL_NETGEN
@@ -3800,6 +3825,51 @@ void series_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)
}
obp->next = obn; /* Restore last link */
// In series runs, all records after the first start with tag "+".
// If the tag got moved to the first record, then move it down to
// the record that is missing the tag.
obn = ob1->next;
if (!strcmp(obn->instance.props[0].key, "_tag")) {
char *tmpkey;
struct valuelist *kv2;
int l;
if (!strcmp(obn->instance.props[0].value.string, "+")) {
/* Remove this property tag "+" */
FREE(obn->instance.props[0].key);
FREE(obn->instance.props[0].value.string);
for (p = 0;; p++) {
obn->instance.props[p].key = obn->instance.props[p + 1].key;
obn->instance.props[p].type = obn->instance.props[p + 1].type;
obn->instance.props[p].value = obn->instance.props[p + 1].value;
if (obn->instance.props[p].type == PROP_ENDLIST) break;
}
for (i = 1; i < run; i++) {
obn = obn->next;
if (strcmp(obn->instance.props[0].key, "_tag")) {
for (p = 1;; p++)
if (obn->instance.props[p].type == PROP_ENDLIST) break;
/* Create a new property record to hold all the existing */
/* properties plus the tag at the beginning. */
kv2 = (struct valuelist *)MALLOC((p + 2) * sizeof(struct valuelist));
kv2->key = strsave("_tag");
kv2->type = PROP_STRING;
kv2->value.string = (char *)MALLOC(2);
kv2->value.string[0] = '+';
kv2->value.string[1] = '\0';
for (l = 0; l <= p; l++)
kv2[l + 1] = obn->instance.props[l];
FREE(obn->instance.props);
obn->instance.props = kv2;
break;
}
}
}
}
FREE(proplist);
}
@@ -4110,8 +4180,8 @@ void PropertySortAndCombine(struct objlist *pre1, struct nlist *tp1,
max2 = 0;
for (c2 = netwk2; ; c2++) {
if (*c2 == 'D') {
cnt++;
run++;
cnt++;
}
else {
if (run > max2) {
@@ -4393,7 +4463,7 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
// Now combine records with same properties by summing M (S).
if (comb == FALSE) {
for (i = 0; i < run - 1; i++) {
for (j = 1; j < run; j++) {
for (j = i + 1; j < run; j++) {
pmatch = 0;
for (p = 1; p < pcount; p++) {
kl = plist[p];
@@ -4411,12 +4481,13 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
if (vl == NULL) {
if (kl->type != vlist[p][j]->type)
PromoteProperty(kl, vl2);
vl = &dfltvl;
}
else {
if (kl->type != vlist[p][i]->type)
PromoteProperty(kl, vl);
vl2 = &dfltvl;
}
vl = &dfltvl;
dfltvl.type = kl->type;
switch (kl->type) {
case PROP_STRING:
@@ -4532,7 +4603,6 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
vlist[0][j]->value.ival = 0;
}
}
else j++;
}
}
}
@@ -6544,7 +6614,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
int result = 1, haspins = 0;
int hasproxy1 = 0, hasproxy2 = 0;
int needclean1 = 0, needclean2 = 0;
char ostr[89];
char *ostr;
#ifdef TCL_NETGEN
Tcl_Obj *mlist, *plist1, *plist2;
#endif
@@ -6583,20 +6653,22 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
}
#endif
ostr = CALLOC(right_col_end + 2, sizeof(char));
if (Debug == 0) {
/* Format side-by-side comparison of pins */
Fprintf(stdout, "\nSubcircuit pins:\n");
*(ostr + 43) = '|';
*(ostr + 87) = '\n';
*(ostr + 88) = '\0';
for (i = 0; i < 43; i++) *(ostr + i) = ' ';
for (i = 44; i < 87; i++) *(ostr + i) = ' ';
snprintf(ostr, 43, "Circuit 1: %s", tc1->name);
snprintf(ostr + 44, 43, "Circuit 2: %s", tc2->name);
for (i = 0; i < 88; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
*(ostr + left_col_end) = '|';
*(ostr + right_col_end) = '\n';
*(ostr + right_col_end + 1) = '\0';
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
snprintf(ostr, left_col_end, "Circuit 1: %s", tc1->name);
snprintf(ostr + left_col_end + 1, left_col_end, "Circuit 2: %s", tc2->name);
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
for (i = 0; i < 43; i++) *(ostr + i) = '-';
for (i = 44; i < 87; i++) *(ostr + i) = '-';
for (i = 0; i < left_col_end; i++) *(ostr + i) = '-';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = '-';
Fprintf(stdout, ostr);
}
@@ -6627,6 +6699,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
TCL_APPEND_VALUE | TCL_LIST_ELEMENT);
}
#endif
FREE(ostr);
return 1;
}
@@ -6636,14 +6709,14 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
if ((IsPort(ob2))
&& (*matchfunc)(ob2->name, obp->name)) {
if (Debug == 0) {
for (m = 0; m < 43; m++) *(ostr + m) = ' ';
for (m = 44; m < 87; m++) *(ostr + m) = ' ';
snprintf(ostr, 43, "%s", obn->name);
for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
snprintf(ostr, left_col_end, "%s", obn->name);
if ((*matchfunc)(obn->name, obp->name))
snprintf(ostr + 44, 43, "%s", obp->name);
snprintf(ostr + left_col_end + 1, left_col_end, "%s", obp->name);
else
snprintf(ostr + 44, 43, "%s **Mismatch**", obp->name);
for (m = 0; m < 88; m++)
snprintf(ostr + left_col_end + 1, left_col_end, "%s **Mismatch**", obp->name);
for (m = 0; m < right_col_end + 1; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
Fprintf(stdout, ostr);
}
@@ -6674,11 +6747,11 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
// so don't print out the "no pins" entry.
if (strcmp(obn->name, "(no pins)")) {
for (m = 0; m < 43; m++) *(ostr + m) = ' ';
for (m = 44; m < 87; m++) *(ostr + m) = ' ';
for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
snprintf(ostr, 32, "%s", obn->name);
snprintf(ostr + 44, 43, "(no matching pin)");
for (m = 0; m < 88; m++)
snprintf(ostr + left_col_end + 1, left_col_end, "(no matching pin)");
for (m = 0; m < right_col_end + 1; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
Fprintf(stdout, ostr);
}
@@ -6701,7 +6774,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
/* Make a pass through circuit 1 to find out if */
/* the pin really is connected to anything, or */
/* has been left orphaned after flattening. If */
/* disconnected, set its node number to -1. */
/* disconnected, set its node number to -2. */
for (obt = ob1->next; obt; obt = obt->next) {
if (obt->type >= FIRSTPIN)
@@ -6709,7 +6782,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
break;
}
if (obt == NULL) {
ob1->node = -1; // Will run this through cleanuppins
ob1->node = -2; // Will run this through cleanuppins
needclean1 = 1;
}
}
@@ -6719,11 +6792,11 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
if (ob1 == NULL) {
if (Debug == 0) {
for (m = 0; m < 43; m++) *(ostr + m) = ' ';
for (m = 44; m < 87; m++) *(ostr + m) = ' ';
snprintf(ostr, 43, "%s", obn->name);
snprintf(ostr + 44, 43, "(no matching pin)");
for (m = 0; m < 88; m++)
for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
snprintf(ostr, left_col_end, "%s", obn->name);
snprintf(ostr + left_col_end + 1, left_col_end, "(no matching pin)");
for (m = 0; m < right_col_end + 1; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
Fprintf(stdout, ostr);
}
@@ -6773,11 +6846,11 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
*(cover + i) = (char)1;
if (Debug == 0) {
for (m = 0; m < 43; m++) *(ostr + m) = ' ';
for (m = 44; m < 87; m++) *(ostr + m) = ' ';
snprintf(ostr, 43, "%s", ob1->name);
snprintf(ostr + 44, 43, "%s", ob2->name);
for (m = 0; m < 88; m++)
for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
snprintf(ostr, left_col_end, "%s", ob1->name);
snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
for (m = 0; m < right_col_end + 1; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
Fprintf(stdout, ostr);
}
@@ -6823,11 +6896,11 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
if (Debug == 0) {
// See above for reverse case
if (strcmp(ob2->name, "(no pins)")) {
for (m = 0; m < 43; m++) *(ostr + m) = ' ';
for (m = 44; m < 87; m++) *(ostr + m) = ' ';
snprintf(ostr, 43, "(no matching pin)");
snprintf(ostr + 44, 43, "%s", ob2->name);
for (m = 0; m < 88; m++)
for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
snprintf(ostr, left_col_end, "(no matching pin)");
snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
for (m = 0; m < right_col_end + 1; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
Fprintf(stdout, ostr);
}
@@ -6856,7 +6929,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
break;
}
if (obt == NULL) {
ob2->node = -1; // Will run this through cleanuppins
ob2->node = -2; // Will run this through cleanuppins
needclean2 = 1;
continue;
}
@@ -6958,6 +7031,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
else if (ob1 != NULL && ob1->type == PORT) {
/* Disconnected node was not meaningful, has no pin match in */
/* the compared circuit, and so should be discarded. */
ob1->node = -2;
needclean1 = 1;
/* Adjust numbering around removed node */
@@ -6970,7 +7044,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
FREE(cover);
if (Debug == 0) {
for (i = 0; i < 87; i++) *(ostr + i) = '-';
for (i = 0; i < right_col_end; i++) *(ostr + i) = '-';
Fprintf(stdout, ostr);
}
@@ -7077,6 +7151,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
}
#endif
FREE(ostr);
return result;
}
+3
View File
@@ -8,6 +8,9 @@ extern struct nlist *Circuit2;
extern int ExhaustiveSubdivision;
extern int left_col_end;
extern int right_col_end;
#ifdef TCL_NETGEN
#include <tcl.h>
extern int InterruptPending;
+1
View File
@@ -673,6 +673,7 @@ char *strdtok(char *pstring, char *delim1, char *delim2)
/* accordingly (needs to be done). */
if (*s == '\\') {
s++;
while (*s != '\0') {
if ((*s == ' ') || (*s == '\\')) {
s++;
+6 -3
View File
@@ -801,9 +801,12 @@ void DescribeInstance(char *name, int file)
{
if (ob->node > nodemax) nodemax = ob->node;
else if ((ob->node == -1) && (ob->model.port != PROXY)) {
if (disconnectednodes == 0) Fprintf(stderr, "\n");
disconnectednodes++;
Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
if (!(tp->flags & CELL_PLACEHOLDER))
{
if (disconnectednodes == 0) Fprintf(stderr, "\n");
disconnectednodes++;
Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
}
}
}
instlist = (unsigned char *) CALLOC((nodemax + 1), sizeof(unsigned char));
+8 -4
View File
@@ -1983,11 +1983,15 @@ void IncludeSpice(char *fname, int parent, struct cellstack **CellStackPtr,
if (strchr(fname, '.') == NULL) {
SetExtension(name, fname, SPICE_EXTENSION);
filenum = OpenParseFile(name, parent);
}
if (filenum < 0) {
Fprintf(stderr,"Error in SPICE file include: No file %s\n",name);
return;
if (filenum < 0) {
Fprintf(stderr, "Error in SPICE file include: No file %s\n", name);
return;
}
}
else {
Fprintf(stderr, "Error in SPICE file include: No file %s\n", fname);
return;
}
}
}
ReadSpiceFile(fname, parent, CellStackPtr, blackbox);
+40 -8
View File
@@ -283,7 +283,7 @@ int GetBusTok(struct bus *wb)
int GetBus(char *astr, struct bus *wb)
{
char *colonptr, *brackstart, *brackend, *sigend, sdelim;
char *colonptr, *brackstart, *brackend, *sigend, sdelim, *aastr;
int result, start, end;
if (wb == NULL) return 0;
@@ -325,15 +325,22 @@ int GetBus(char *astr, struct bus *wb)
return 0;
}
brackstart = strchr(astr, '[');
// Delimiters may appear in backslash-escaped names. . . ignore these.
aastr = astr;
if (*aastr == '\\') {
aastr++;
while (*aastr != ' ' && *aastr != '\\' && *aastr != '\0') aastr++;
}
brackstart = strchr(aastr, '[');
if (brackstart != NULL) {
brackend = strchr(astr, ']');
brackend = strchr(aastr, ']');
if (brackend == NULL) {
Printf("Badly formed array notation \"%s\"\n", astr);
return 1;
}
*brackend = '\0';
colonptr = strchr(astr, ':');
colonptr = strchr(aastr, ':');
if (colonptr) *colonptr = '\0';
result = sscanf(brackstart + 1, "%d", &start);
if (colonptr) *colonptr = ':';
@@ -1558,19 +1565,40 @@ nextinst:
// Check if net name is a wire bus or portion of a bus
if (GetBus(scan->net, &wb) == 0) {
int range;
// This takes care of three situations:
// (1) The signal bus length matches the number of instances:
// apply one signal per instance.
// (2) The signal bus length is a multiple of the number of instances:
// apply a signal sub-bus to each instance.
// (3) The number of instances is a multiple of the signal bus length:
// apply the same signal to each instance.
if ((arrayend - arraystart) == (wb.end - wb.start)) {
// Net is a bus, but net is split over arrayed instances
Port(scan->name);
}
else if (wb.start > wb.end) {
range = wb.start - wb.end;
if ((arraystart - arrayend) > (wb.start - wb.end))
range = (((arraystart - arrayend) + 1) /
((wb.start - wb.end) + 1)) - 1;
else
range = (((wb.start - wb.end) + 1) /
((arraystart - arrayend) + 1)) - 1;
for (i = range; i >= 0; i--) {
sprintf(defport, "%s[%d]", scan->name, i);
Port(defport);
}
}
else {
range = wb.end - wb.start;
if ((arrayend - arraystart) > (wb.end - wb.start))
range = (((arrayend - arraystart) + 1) /
((wb.end - wb.start) + 1)) - 1;
else
range = (((wb.end - wb.start) + 1) /
((arrayend - arraystart) + 1)) - 1;
for (i = 0; i <= range; i++) {
sprintf(defport, "%s[%d]", scan->name, i);
Port(defport);
@@ -2036,11 +2064,15 @@ void IncludeVerilog(char *fname, int parent, struct cellstack **CellStackPtr,
if (strchr(fname, '.') == NULL) {
SetExtension(name, fname, VERILOG_EXTENSION);
filenum = OpenParseFile(name, parent);
if (filenum < 0) {
fprintf(stderr,"Error in Verilog file include: No file %s\n", name);
return;
}
}
if (filenum < 0) {
else {
fprintf(stderr,"Error in Verilog file include: No file %s\n", fname);
return;
}
}
}
}
ReadVerilogFile(fname, parent, CellStackPtr, blackbox);
+1 -1
View File
@@ -25,7 +25,7 @@ install-tcl: netgenexec${EXEEXT} $(DESTDIR)${INSTALL_BINDIR}/netgen.sh ${TCL_FIL
netgenexec${EXEEXT}: netgenexec.c
${CC} ${CFLAGS} ${CPPFLAGS} ${DFLAGS_NOSTUB} netgenexec.c \
-o netgenexec${EXEEXT} \
${LDFLAGS} ${LIBS} ${LIB_SPECS_NOSTUB}
${LIB_SPECS_NOSTUB} ${LDFLAGS} ${LIBS} ${GR_LIBS}
netgen.tcl: netgen.tcl.in
sed -e 's%TCL_DIR%${TCLDIR}%g' \
+86 -7
View File
@@ -85,6 +85,7 @@ int _netcmp_compare(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_iterate(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_summary(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_print(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_format(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_run(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_verify(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_automorphs(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
@@ -199,6 +200,9 @@ Command netcmp_cmds[] = {
{"print", _netcmp_print,
"\n "
"print netcomp internal data structure"},
{"format", _netcmp_format,
"<col1_width> <col2_width>\n "
"set width of formatted output"},
{"run", _netcmp_run,
"[converge|resolve]\n "
"converge: run netcomp to completion (convergence)\n "
@@ -1971,6 +1975,61 @@ _netgen_printmem(ClientData clientData,
}
#endif
/*------------------------------------------------------*/
/* Function name: _netcmp_format */
/* Syntax: */
/* netgen::format [col1_width [col2_width]] */
/* Formerly: (none) */
/* Results: */
/* Side Effects: */
/*------------------------------------------------------*/
int
_netcmp_format(ClientData clientData,
Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
{
int col1_width = 41, col2_width = 41;
if (objc > 1) {
if (Tcl_GetIntFromObj(interp, objv[1], &col1_width) != TCL_OK)
return TCL_ERROR;
if (objc > 2) {
if (Tcl_GetIntFromObj(interp, objv[2], &col2_width) != TCL_OK)
return TCL_ERROR;
} else {
/* If only one argument is given, then apply it to both columns */
col2_width = col1_width;
}
if (col1_width <= 0 || col2_width <= 0) {
Tcl_SetResult(interp, "Column width cannot be zero or less\n", NULL);
}
// Default values for left and right columns are 43 and 87
left_col_end = col1_width + 2;
right_col_end = left_col_end + col2_width + 3;
}
else if (objc == 1) {
Tcl_Obj *lobj, *tobj;
col1_width = left_col_end - 2;
col2_width = right_col_end - col1_width - 5;
lobj = Tcl_NewListObj(0, NULL);
tobj = Tcl_NewIntObj(col1_width);
Tcl_ListObjAppendElement(interp, lobj, Tcl_NewIntObj(col1_width));
Tcl_ListObjAppendElement(interp, lobj, Tcl_NewIntObj(col2_width));
Tcl_SetObjResult(interp, lobj);
return TCL_OK;
}
else {
Tcl_WrongNumArgs(interp, 1, objv, "[col1_width [col2_width]]");
return TCL_ERROR;
}
}
/*------------------------------------------------------*/
/* The following code breaks up the NETCOMP() command */
/* from netcmp.c into individual functions w/arguments */
@@ -2900,15 +2959,35 @@ _netcmp_equate(ClientData clientData,
case PINS_IDX:
if ((ElementClasses == NULL) && (auto_blackbox == FALSE)) {
if (CurrentCell == NULL)
if (CurrentCell == NULL) {
Fprintf(stderr, "Equate elements: no current cell.\n");
Fprintf(stderr, "Equate pins: cell %s and/or %s has no elements.\n",
name1, name2);
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
return TCL_OK;
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
return TCL_OK;
}
else if ((tp1->flags & CELL_PLACEHOLDER) ||
(tp2->flags & CELL_PLACEHOLDER)) {
if (tp1->flags & CELL_PLACEHOLDER) {
Fprintf(stdout, "Warning: Equate pins: cell %s "
"has no definition, treated as a black box.\n", name1);
}
if (tp2->flags & CELL_PLACEHOLDER) {
Fprintf(stdout, "Warning: Equate pins: cell %s "
"has no definition, treated as a black box.\n", name2);
}
// If a cell in either circuit is marked as a black box, then
// the cells in both circuits should be marked as a black box.
tp1->flags |= CELL_PLACEHOLDER;
tp2->flags |= CELL_PLACEHOLDER;
}
else {
Fprintf(stdout, "Equate pins: cell %s and/or %s "
"has no elements.\n", name1, name2);
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
return TCL_OK;
}
}
else if (ElementClasses == NULL) {
/* This has been called outside of a netlist compare, */
if (ElementClasses == NULL) {
/* This may have been called outside of a netlist compare, */
/* probably to force name matching of pins on black-box */
/* devices. But MatchPins only works if tp1 == Circuit1 */
/* and tp2 == Circuit2, so preserve these values and */