Commit Graph

831 Commits

Author SHA1 Message Date
Tim Edwards f02802dd21 Merge branch 'master' into netgen-1.5 2026-04-03 02:00:04 -04:00
R. Timothy Edwards 0192558d4b Updated version corresponding to the last commit. 2026-04-02 21:30:01 -04:00
R. Timothy Edwards 21d329b22d Modified the hash algorithm used by netgen after a discussion with
ChatGPT about hash implementations.  Switched from SDBM to FNV-1a,
which should be a better/stronger hash algorithm.  Could do
something more sophisticated, but this change can be done in a few
minutes.
2026-04-02 21:29:04 -04:00
Tim Edwards b76c9a1712 Merge branch 'master' into netgen-1.5 2026-02-03 02:00:02 -05:00
R. Timothy Edwards 37b1a2a07d Cleaned up some errors (most minor, some not so minor) in the
code that were surfaced by Stefan Thiede running clang on Mac
OS.  Function prototype warnings have not been fixed yet, as
that is a more involved fix, although it needs to be done.
2026-02-02 20:53:13 -05:00
Tim Edwards 4d44abcca4 Merge branch 'master' into netgen-1.5 2026-01-16 02:00:02 -05:00
R. Timothy Edwards 777f7ef095 Found a counting issue with netcmp output that will overrun the
output string buffer if the size of the copied string is just
the wrong amount, due to the use of strcpy() instead of
strncpy() in at least one place.  Just hacked a solution by
allocating more space for the string, but this should be fixed
properly.  Also:  Discovered that the "zero valued resistor"
routine looks for shorted ports in the wrong place, and if it
finds shorted ports it wrongly decides that the device it's
looking at is a zero-valued resistor whether or not it really
is zero-valued.
2026-01-15 16:39:18 -05:00
Tim Edwards 29ee16644d Merge branch 'master' into netgen-1.5 2025-12-29 02:00:02 -05:00
R. Timothy Edwards 9b4185fe62 Reverted a change from a long time ago regarding removal of zero
valued resistors connecting two ports.  I do not recall exactly
why I put that in but it appears to cause incorrect behavior.
2025-12-28 14:54:07 -05:00
Tim Edwards f5147e5af6 Merge branch 'master' into netgen-1.5 2025-12-12 02:00:03 -05:00
R. Timothy Edwards ddd95c4fe6 Added a few lines to the setup file parser so that if there is a
missing brace in the file (a common error), then the fact that
there is an unevaluated command when the file has finished being
read will trigger an evaluation of the unfinished code and emit
an error.  Previously, the command and anything after the
unterminated brace would just silently get ignored, which was not
helpful for debugging setup syntax errors.
2025-12-11 12:08:31 -05:00
Tim Edwards 23b4e19204 Merge branch 'master' into netgen-1.5 2025-12-09 02:00:02 -05:00
R. Timothy Edwards c0c9993980 Corrected a major error with the verilog parser. The verilog
parser was not assigning the correct file number for the first
input file, which resulted in the effect that if the first
file read sets definitions for the netlist, then those definitions
are wiped out on the following file read.  There has been a workaround
to read from /dev/null on the first file read so that the file number
is set on all subsequent reads.  This fix avoids the need for the
workaround.
2025-12-08 16:45:27 -05:00
R. Timothy Edwards 8a20b90074 Corrected an issue that can cause a segfault in an incorrect run
setup when a cell has no pins.  Didn't really analyze the error
condition, just caught and handled the condition to avoid the
segfault.
2025-12-08 13:09:50 -05:00
Tim Edwards 5bb279a9e4 Merge branch 'master' into netgen-1.5 2025-11-30 02:00:04 -05:00
R. Timothy Edwards 3392159243 Added some extra code to the verilog parser. It now handles some
additional syntax for wire bundles specified as a pin connection
on an array of instances, and a few other things.  These are not
exhaustive but are solving an immediate problem.  I will go back
and clean up the code to make it work for more general cases
later.
2025-11-29 11:55:26 -05:00
Tim Edwards b2662b443f Merge branch 'master' into netgen-1.5 2025-11-25 02:00:02 -05:00
R. Timothy Edwards 24c6eb4cb9 Updated the version to go along with the merge of pull request 2025-11-24 12:26:57 -05:00
Mitch Bailey 9048191486 Allow processing of cellnames with $.
When loading a file, also print cellname on errors

Signed-off-by: Mitch Bailey <d.mitch.bailey@gmail.com>
2025-11-24 12:26:30 -05:00
Tim Edwards 1acef6c52c Merge branch 'master' into netgen-1.5 2025-11-22 02:00:02 -05:00
R. Timothy Edwards 72d7d55bbe Corrected an issue with the "-noflatten" switch to "lvs", which is
also a problem with the underlying "flatten prohibit" command
option;  in one place, the cell's subcircuits were being prohibited
from being flattened, causing issues including a potential infinite
loop.
2025-11-21 15:52:14 -05:00
Tim Edwards 7459b6dfe8 Merge branch 'master' into netgen-1.5 2025-11-13 02:00:02 -05:00
R. Timothy Edwards 04163aedcc One hopefully final modification to ensure that Tcl_InitStubs()
uses the Tcl version that the program has been compiled to.  This
should work with both Tcl 8.X and Tcl 9.X.
2025-11-12 11:32:18 -05:00
R. Timothy Edwards f7d35f9cca Accidentally changed a file in the last commit which gets
overwritten by "configure".  Moved the modification to the source
file that doesn't get overwritten.
2025-11-12 09:55:29 -05:00
R. Timothy Edwards 601277e539 Updated the revision number for the last set of changes. 2025-11-12 09:19:52 -05:00
R. Timothy Edwards 73344329f8 Made some updates for Tcl 9 compatibility; also changed the
Makefile to pass EXTRA_CFLAGS for testing with "-std=c99" and
"-std=gnu99".  Made some additional corrections to ensure a
clean compile using -std=gnu99.
2025-11-12 09:17:46 -05:00
Tim Edwards 7f2ab31143 Merge branch 'master' into netgen-1.5 2025-11-12 02:00:02 -05:00
R. Timothy Edwards 08485d28a7 Changed CONST and CONST84 everywhere in tclnetgen.c to "const".
The capitalized version of this got removed from the Tcl headers
as some point and is no longer valid.  Added an include of
"strings.h" to base/actel.c, which was missing it (uses
strcasecmp() in the code, and needs the function declaration).
2025-11-11 09:59:14 -05:00
Tim Edwards 45164bbf98 Merge branch 'master' into netgen-1.5 2025-11-08 02:00:04 -05:00
R. Timothy Edwards 2ee286efb4 Corrected the pin permutation check for pin matching; previously,
this was not doing the correct cross-check, instead looking in the
same netlist for the permutable pin and checking its node number,
which is useless since the node number is the same by definition
for permutable pins.  This error would result in occasional false
negative results during pin matching, showing matching where pins
are actually not matched.
2025-11-07 14:06:22 -05:00
Tim Edwards 46cb8d6637 Merge branch 'master' into netgen-1.5 2025-10-24 02:00:04 -04:00
R. Timothy Edwards dae6919d4f Updating the version to go along with the merge of pull request 2025-10-23 09:54:36 -04:00
D. Mitch Bailey 017bdc6e48 Changed nested to static variable. Otherwise gets reset with each line.
Signed-off-by: D. Mitch Bailey <d.mitch.bailey@gmail.com>
2025-10-23 08:30:08 +00:00
Tim Edwards 2825b786b7 Merge branch 'master' into netgen-1.5 2025-10-23 02:00:04 -04:00
R. Timothy Edwards b371af9235 Corrected an error that was assumed to have been fixed three years
ago (and may have been, but only under limited circumstances).  Do
to several errors, using "-noflatten" on the command line and using
"flatten prohibit" in a script would not prevent cells from being
flattened;  the "-noflatten" list needed to be used to call "flatten
prohibit", and "flatten prohibit" needed to be fixed to flag the
specified cell instead of the top level cell where it exists.
2025-10-22 10:43:00 -04:00
Tim Edwards 0af8c7ad49 Merge branch 'master' into netgen-1.5 2025-10-10 02:00:03 -04:00
R. Timothy Edwards b5432d139b Corrected a corner-case where a module with no ports in verilog
was creating an implicit net for the stand-in "(no pins)" port.
2025-10-09 10:36:41 -04:00
Tim Edwards 0aa20dcf62 Merge branch 'master' into netgen-1.5 2025-10-09 02:00:04 -04:00
R. Timothy Edwards 0e958bd45c Corrected an issue in which black-box entries (such as low-level
subcircuit devices) do not output information about mismatched
pins.  This can end up being treated as a non-error but the
mismatch should be noted in the output regardless.
2025-10-08 10:03:35 -04:00
Tim Edwards 7cbf15aab1 Merge branch 'master' into netgen-1.5 2025-10-03 02:00:02 -04:00
R. Timothy Edwards b59196fa81 Modified the SPICE file read routine to accept the CDL syntax
"*.GLOBAL" as equivalent to ".GLOBAL".  Corrected the property
matching to handle property combination when no "critical"
property is given.  Critical properties exist when one property
must remain constant and equal for other properties to combine,
such as transistor length.  But, for example, capacitors can
combine area without any restriction based on another property.
Also, corrected the property matching code to allow more than
one property to be additive (example:  capacitor area and
perimeter).  Corrected the equation for adding properties in
parallel combination.
2025-10-02 12:33:28 -04:00
Tim Edwards 1de6f88f1e Merge branch 'master' into netgen-1.5 2025-09-10 02:00:02 -04:00
R. Timothy Edwards 6e6e9fb73f Added code to catch and print an error in connectivity between a
port and an internal node which can be missed when pin permutations
are present.  Previously, that could produce a situation where
netgen would report a "port error" but otherwise list all ports
as matching.  Because the permutation handling makes this hard to
detect while generating pin correspondence output, the non-matching
pins are listed separately at the end, and only if no mismatch was
detected during output.
2025-09-09 13:45:29 -04:00
Tim Edwards 33fed391fd Merge branch 'master' into netgen-1.5 2025-09-01 02:00:02 -04:00
R. Timothy Edwards e84700a607 Added a NULL check at one point in the SPICE read routine that
prevents a segfault under some condition (not fully investigated)
involving .include files.  Appears to resolve the problem without
any unintended consequences.
2025-08-31 16:52:35 -04:00
Tim Edwards 5f5248b3d0 Merge branch 'master' into netgen-1.5 2025-08-27 02:00:03 -04:00
R. Timothy Edwards 0bee21ccc8 Corrected an issue in which a property error in a subcell would not
be reported at the end if there was a port error.  This is important
because port errors often resolve themselves, but the cell should not
be reported clean if the port errors resolved but it had property
errors.  Also:  Added a method to derive area and/or perimeter
properties from length and width, so that capacitors can be combined
in parallel without regard to which dimension is width and which is
length.  This feature has only been lightly tested.
2025-08-26 17:47:46 -04:00
Tim Edwards 80f9263004 Merge branch 'master' into netgen-1.5 2025-08-26 02:00:02 -04:00
R. Timothy Edwards c269f1de89 Corrected an unexpected corner-case error in which if a newline in
a spice netlist falls exactly on the last non-null position of the
input buffer after the buffer has been expanded to accept more
input data, then the next line gets read in automatically, and
the newline gets treated as whitespace and not a newline.
2025-08-25 10:31:19 -04:00
Tim Edwards edb50746cb Merge branch 'master' into netgen-1.5 2025-08-19 02:00:02 -04:00