handle verilog syntax. Also: Added SPICE voltage and current
sources as separate classes (as opposed to being converted to
subcircuits, which was how they were previously handled). That
allowed voltage sources to be checked for zero value and removed
by shorting the ends together, as was being done for zero value
resistors (note that like zero-value resistors, removal is only
done if removing the component makes a better match than leaving
it in). In particular, yosys has SPICE netlist output that
converts equality assignments ("assign a = b") into zero-value
voltage sources, so these components need to be treated as
non-physical elements.
the possibility that a device (e.g., resistor or capacitor) may
not be a semiconductor device (in other words, a parasitic or
ideal device), and therefore uses "value" but not width and
length, and therefore "value" is a critical property to merge
both in series and parallel. Corrected the series/parallel
network optimization to prevent it from setting both M and S
records > 1 on the same device (which is ambiguous). To try
to get number of devices to match, where there are both series
and parallel devices, they will be merged across the critical
property early (before property matching).
type double before sorting (previously, property promotion was
being done after parallel sorting). Also, modified the verilog
file reading so that parameters and definitions that are numeric
are stored as numeric (not string) properties.
determine if a parameter is a floating-point number, integer, or
string, and set the parameter accordingly. Found an error in the
parameter comparison if the subcircuit definitions don't agree
on the type of parameter. Now all values are promoted to a single
type based on preference order (double, integer, string). Tested
on a verilog file with a primitive device type defined as a module
with its properties encoded as parameters. This successfully
matched against the SPICE primitive device.
be in any specific order since all ports are named. Also corrected
problem with pin names not using the same string matching function
as used for nets in general (which affects the ability to match
against different bus delimiters).
some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one. Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).
calls "equate pins". This could fail because the routine that forces
uniqueness of pins was being called by the "compare" command but
outside of PinMatch. Fixed by duplicating the call to force uniqueness
of pins inside the "equate" function. Redundant calls should not
matter as uniqueness is resolved on the first call and subsequent calls
will need no further action.
time warnings and errors. Removed the "-lazy" option from the
Tcl load command, which is not needed when the stubs libraries
are compiled in correctly, and which causes issues on some
systems (e.g., Mac OS). Thanks to Matt Guthaus for the patch.
the default before comparing instances against each other for
serial/parallel combination. In particular, this avoids a
failure to serially combine a device with M = 1 vs. a device with
no M declared.
Netgen was incorrectly treating mismatched networks as a missing
set of parameters on whichever device had more property records,
resulting in misleading output.
attempt to resolve values by combining over serial chains was
attempting to access a property "S" in the component's master
record, which generally won't exist unless it has been explicitly
set in the netlist (which is unlikely since "S" is not a standard
SPICE/CDL parameter like "M").
unordered at the time of reaching reorderpins(). Pins will be
ordered arbitrarily (in the order of appearance in the linked
list), but netgen will not crash.
for subcircuits (.subckt ... .ends pair with cellname and pin names
and pin order, but no contents) are automatically treated as black-
box circuits if found and if the "-blackbox" option is passed to the
"lvs" (scripted) command. The "equate pins" command can be used
outside of a comparison to force two circuits (black-box or
otherwise) to be matched by pin name (if not a black-box circuit,
then this is a provisional name match, as a circuit comparison will
order based on connectivity first, not pin names). So two sets of
black-box circuit libraries can be used as long as their pin names
match. One hack added to ignore the "!" at the end of global names
when comparing pin names for matching. Otherwise, pin names must
compare by case-insensitive string match.
about property errors to show up, not due to property errors, but
due to proxy pins being inserted in the middle of a device record.
However, the first one was fixed for the case of proxy pins being
added to circuit 1, but the same fix was not made for the opposite
case of proxy pins being added to circuit 2. This commit corrects
that omission.
to stop at the end of an instance record without properties, leading
to strange errors where netgen declares "There were property errors"
but does not print any errors (because there aren't any).
the serial combination routine was disabled so as not to post a
non-working version, since the parallel/serial property networks
are not analyzed. This should be completed soon.
making any subcircuit serializable by using the new command option
"property (device) serial|parallel enable|disable". Note that as
of this commit, serial device detection is enabled but serial
networks are not collapsed for matching, which will tend to lead
to property errors in serial devices until this code is added,
which should be in a day or two.
an instance property did not match the cell property type, as
long as the cell property types of the two compared cells matched.
Along with a recent change that left "M" as a type double during
SPICE netlist read-in, this caused "M" mismatches to be ignored,
because the double value was ignored and the integer value was
always zero.
avoid the problem where non-critical properties cause devices not
to match, resulting in apparent mismatches of matched devices.
The current behavior now prints a statement about each device.
However, the result is still somewhat ambiguous.
as failing on certain compilers. This undoubtedly reflects some
change in gcc or the OS setup, but since modern compilers should
be able to figure out for themselves when to inline a subroutine
(or not), the inline hint is somewhat arcane and unnecessary.
'ignore class', but removes instances of the specified class whose
pins are shorted together. Currently requires that all pins must
be shorted together.
leading '/' of pin names and therefore failing to print anything;
(2) Corrected 'addproxies', which was ending abruptly at the end of
a circuit's object list, such that if an instance needing proxy pins
added was the last object in the circuit, it would not get the proxy
pins added, and therefore would fail LVS.
include calculations of effective width due to the addition of
width of multiple device instances in parallel. The original
behavior of splitting all "M=" devices into individual instances
has been effectively inverted, instead combining all parallel
devices of the same class into one, with multiple property
records for devices with non-matching properties (e.g., width,
length, etc.). Property matching combines devices with different
"critical properties" (e.g., FET gate width) if these are defined
in the setup using the "property merge" command.
Not yet done: Matching of multiple property records when
critial properties are not defined, handling of critical properties
that combine in parallel instead of simple addition, handling of
devices that combine in series, and the combination of non-critical
properties (e.g., source and drain area, although these are usually
removed from matching).
based on properties that can be traded with number of devices,
such as MOSFET width, by merging. This initial implementation
is somewhat limited, only dealing with properties that merge
by summing. Only devices that do not match at all in the other
circuit will be considered for merging. The feature includes
a command option "property ... merge ..." that allows control
over which devices can and cannot be merged.
variables to iterate over hash table contents. This led to the
inability to nest hash table iterators. Fixed by defining a
wrapper structure that holds the actual hash table plus the size
and iterator indexes. Not only does this solve the nesting
problem, but it also avoids the need to pass the hash table size
on every call, and that reduces the number of ways a hash table
subroutine can go wrong (e.g., cannot access the table out of
bounds simply by passing a size that is larger than was used to
initialize the table).
comparisons between, duplicate cells (cells with the same netlist
that may have more than one name in a circuit, or which for some
reason appear with the same name more than once in a netlist).
Added more checks to the list prematching, which prevents various
troubles with cells having a mismatched hierarchy. Added a
command option to "flatten class" to flatten instances only within
a specific cell. Corrected one error in the pin matching routine.
Added a check in the pin matching routine to look for pins that
have been found to be no-connects after cleaning up the pin lists
of the children of that cell.
equates class "a" in circuit 1 with class "b" in circuit2, and
if circuit 1 has a class called "b" and/or circuit 2 has a class
called "a", then both classes are given a new hash to avoid
conflicts with the (presumably) unrelated cells of the same name
in the other netlist.
comparison would look for matching names from the "equate
classes" command. However, it failed to do the reverse
check, which is to make sure that if no forced match was
found for a cell, but there was a name match, that the
name-matched cell found is not being forcibly matched to
something else.
that matches explicitly called out in the setup file using
"equate classes" will take precedence over same-name matching,
instead of the other way around.
Tim Edwards