Changed line breaks in log and stdout to better differentiate subcircuits.
Added merged series device counts and differentiated from parallel merged device counts.
Added file number to disconnected net, merged count messages.
Changed black box errors to show file numbers instead of hard coded values.
Final error cell list changed from all on one line to one per line.
Removed redundant display in black box warning.
print statement, and clarified the messages about non-matching
circuits at the end, all of them suggestions made by Mitch
Bailey (see issue #34 on github).
saying that pins were mismatched when pin matching was never run
accidentally resulted in pin matching not being applied to black-box
entries. This has been corrected.
pins for enabling parallel combinations, which could cause a crash.
Added a "-force" option to "equate pins" to allow pins to be matched
even on subcircuits that did not correctly match; this was done in
conjuction with an extra option to the "lvs" command "-noflatten="
to pass a list of cellname to not be flattened even if they do not
match. This is generally discouraged, as it prevents netgen from
resolving differences between layout and schematic hierarchy, but it
can be useful for checking that the hierarchy above a certain cell
is correct, given that if a subcell is really unmatched, then its
errors will keep propagating up the top level, making additional
errors hard to diagnose.
the top level circuits to be declared matching with no errors even
though the pins do not match. "proxy pins" are fine for subcells
to detect cases where one subcell has an unused pin and the matching
subcell does not declare it, but that should not be allowed on the
top level, as it cannot be known whether the pin is unused or not.
they are converted to the double-backslash escape that is the proper
JSON syntax for backslashes, instead of being removed, which changes
the name and can be confusing.
in verilog net names, which are apparently legal in verilog but not
in python strings (if not escaped). This is somewhat critical for
running the LVS GUI as yosys can generate backslashes in generated
net names in the synthesized netlist.
be specified as "nosetup" if the "lvs" command is being called
interactively from a terminal or as part of a larger script where
setup commands have been issued prior to running the "lvs" script.
Similarly, the log file can be specified as "nolog" to prevent any
log file from being generated.
time warnings and errors. Removed the "-lazy" option from the
Tcl load command, which is not needed when the stubs libraries
are compiled in correctly, and which causes issues on some
systems (e.g., Mac OS). Thanks to Matt Guthaus for the patch.
for subcircuits (.subckt ... .ends pair with cellname and pin names
and pin order, but no contents) are automatically treated as black-
box circuits if found and if the "-blackbox" option is passed to the
"lvs" (scripted) command. The "equate pins" command can be used
outside of a comparison to force two circuits (black-box or
otherwise) to be matched by pin name (if not a black-box circuit,
then this is a provisional name match, as a circuit comparison will
order based on connectivity first, not pin names). So two sets of
black-box circuit libraries can be used as long as their pin names
match. One hack added to ignore the "!" at the end of global names
when comparing pin names for matching. Otherwise, pin names must
compare by case-insensitive string match.
treat empty subcircuits as blackbox cells automatically without
requiring specific callse to "model <cell> blackbox" for each.
Enabled in LVS script by giving option "-blackbox" at the end
of the LVS command.
leading '/' of pin names and therefore failing to print anything;
(2) Corrected 'addproxies', which was ending abruptly at the end of
a circuit's object list, such that if an instance needing proxy pins
added was the last object in the circuit, it would not get the proxy
pins added, and therefore would fail LVS.
"permute default" by (1) handling the usual case for MOSFETs
(resistors and adding in parallel not yet implemented), and
(2) being done automatically when no setup script is specified.
include calculations of effective width due to the addition of
width of multiple device instances in parallel. The original
behavior of splitting all "M=" devices into individual instances
has been effectively inverted, instead combining all parallel
devices of the same class into one, with multiple property
records for devices with non-matching properties (e.g., width,
length, etc.). Property matching combines devices with different
"critical properties" (e.g., FET gate width) if these are defined
in the setup using the "property merge" command.
Not yet done: Matching of multiple property records when
critial properties are not defined, handling of critical properties
that combine in parallel instead of simple addition, handling of
devices that combine in series, and the combination of non-critical
properties (e.g., source and drain area, although these are usually
removed from matching).
errors at the end of LVS. The result of "verify matching" got
overwritten by the result from matching pins, erasing the information
about a cell having property errors.
comparisons between, duplicate cells (cells with the same netlist
that may have more than one name in a circuit, or which for some
reason appear with the same name more than once in a netlist).
Added more checks to the list prematching, which prevents various
troubles with cells having a mismatched hierarchy. Added a
command option to "flatten class" to flatten instances only within
a specific cell. Corrected one error in the pin matching routine.
Added a check in the pin matching routine to look for pins that
have been found to be no-connects after cleaning up the pin lists
of the children of that cell.
D. Mitch Bailey
Tim Edwards