<col2_width>" to set the output format width, to avoid the fixed column
widths of 41 characters which can truncate long strings in the output
such as deep cell hierarchies. This command can be placed in the setup
script to widen the output columns to accomodate the result (to-do:
provide an "auto" mode to automatically determine the best width).
"prefix" with the specified path during install, so that netgen can
be installed in a separate location to be migrated to the final
install location, without appending the entire install path to
DESTDIR.
they are converted to the double-backslash escape that is the proper
JSON syntax for backslashes, instead of being removed, which changes
the name and can be confusing.
with increment/decrement syntax at the end. Also the parser now
handles additional keywords associated with behavioral verilog
(initial, specify) and flags modules with them as black-box entries.
that affects vectors sliced across instance arrays. Can cause vector
numbers to be out-of-bounds if an instance is arrayed but each
instance is listed separately.
inline-I/O syntax with "wire" (e.g., "input wire [3:0] test")
and addressed the failure to add buses declared in inline I/O
to the list of known buses.
verilog parser. The parser should now be able to handle any
conditionals anywhere in the verilog code. Also a bug was found
in the code that handles "a = b" assignments, and corrected.
code using the backtick expression. Also expanded the parsing of
"ifdef", "ifndef", and "endif" to include "elsif" and "else". All
forms of "if" statements should now be handled, since verilog does
not define boolean expressions in ifdef operators like most languages
do.
SPICE and verilog, in spite of the syntactical differences, to
account for the trick that qflow uses to replace the trailing space
in a verilog backslash-escaped name with a second backslash to get
a SPICE-compatible name that can be easily converted back to its
original verilog name without loss of information. What this means
is that verilog can read SPICE files containing verilog names (which
is illegal SPICE) and verilog files containing hacked-backslash
names (which is illegal verilog). This should be mostly harmless
although the wisdom of it is surely questionable.
assignment statements in verilog netlists, including assignment of
signal bundles. Also corrected handling of signal bundles in pin
connections, which had been corrected in qflow's verilog parser but
not copied back to netgen. Note that the syntax for signals multiplied
N times is still not handled.
Tim Edwards
Roman-Parise