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netgen
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461 Commits

Author SHA1 Message Date
Tim Edwards 625e043eff Made a correction to the flattening code, removed a duplicate 
print statement, and clarified the messages about non-matching
circuits at the end, all of them suggestions made by Mitch
Bailey (see issue #34 on github).
 2021-10-15 09:13:02 -04:00
Tim Edwards 6ceeddf096 Minor syntactical editing of pull request #33, and updated version 
to go along with the merge of the pull request (from Mitch Bailey).
 2021-10-14 11:22:20 -04:00
D. Mitch Bailey 42b1acc564 Flatten unmatched cells that don't contain instances from the other file. 2021-10-13 21:00:49 -07:00
D. Mitch Bailey 6d6da9cf5c Remove disconnected ports after flattening. 2021-10-13 01:15:15 -07:00
Tim Edwards bbcc79fc72 Updated version to go along with merge of pull request #32 from 
Harald Pretl.
 2021-10-05 09:41:24 -04:00
Harald Pretl 6d5946eaf2 Added MacOS (Big Sur) installation instructions. 2021-10-03 13:58:34 +02:00
Tim Edwards 18dcac73bc Updated version to go along with the merge of pull request #31 
from Mitch Bailey.
 2021-09-07 22:27:31 -04:00
D. Mitch Bailey 1338e3beb5 Removed debugging statement. 2021-09-07 19:16:33 -07:00
D. Mitch Bailey df1c4c5153 Changed debug print increment from 100 -> 10000. 2021-09-07 10:19:27 -07:00
D. Mitch Bailey a05ede99db Added missing newlines 
Print debug message every 100 lines
 2021-09-06 18:31:38 -07:00
D. Mitch Bailey 2d6f1f71b5 Reduce and clarify debugging message. 
Add missing new line to "Flattening non-matched subcircuits.
 2021-09-02 22:29:17 -07:00
Tim Edwards d7355cea95 Updated the vezzal docker image version for CI. 2021-08-29 19:41:14 -04:00
Tim Edwards 32585a572c Corrected the badge link at the top of README.md to point to my 
own repository instead of a fork.
 2021-08-28 13:14:11 -04:00
Tim Edwards e773739e7d Updated VERSION as a forced change to check continuous integration 
on github.
 2021-08-06 11:37:29 -04:00
Tim Edwards 583cc3a151 Updated VERSION to go along with the merge of pull request #27 from 
Sai Charan.  Subsequent mirror pushes to github should trigger the
continuous integration.
 2021-08-06 11:18:56 -04:00
Sai Charan Lanka bdd7d25943 Update main.yml 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 903b813821 Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 1f9d4317e3 Update main.yml 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 7b8086fc3a Update main.yml 2021-08-06 11:18:32 -04:00
Sai Charan Lanka e80f70e67b Update main.yml 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 6cc898b34b Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 30bbc28c17 Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 5ec0db678a Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka e643563d4e Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 67f2801aa1 Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka f76f2e002a Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 9ec613b0cb Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 9128eeda60 Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka aeedf5fae9 Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka f50dfd9261 Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 409ce224ad Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka f50093e6c6 Rename README to README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka a27ac8c679 Update README 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 883755eed3 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 484cb26eee Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 7cc6996017 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 7f9acf6a1a Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka e1a3ae5619 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 4e75889605 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka e017811239 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 4468d36462 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka b99fb96259 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka ec8299ea14 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 376296eda5 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 30acb8be63 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 7e15a26417 Create main.yml 2021-08-06 11:18:31 -04:00
Tim Edwards 21750da6c4 Corrected the Makefile in the python directory to set the 
lvs_manager.py script to be executable, or else "netgen -gui" will
not work.
 2021-07-29 10:45:44 -04:00
Tim Edwards a332c23524 Corrected an error in "series_sort" that will overwrite memory 
randomly if combining series devices that do not have an "S"
property (which is the typical case).  This will normally result in
a crash.
 2021-07-15 16:03:43 -04:00
Tim Edwards 064195ecc9 Reinstated some code that had been commented out that prints pin 
information for a non-matching pin in circuit1 and generates a
proxy pin in circuit2---there is some case where this is redundant,
I think, but I need to find the example.
 2021-07-11 17:04:50 -04:00
Tim Edwards 88d53fab15 Correction to the verilog parser to recognize modifiers such as 
"~", "!", or "-" in front of variable names in a pin list that would
render the module behavioral verilog.
 2021-07-11 12:06:16 -04:00