tracker #96) in which a subcircuit with only one port (in this
case, a pad) but which has properties (in this case, "M") will
fail to set the pointer position ahead of the property because
the loop starts after the first pin, so it has already missed
the position that needs to be saved. Fixed by initializing
the value to the first pin position before starting the loop.
to be caused by failing to have a systematic way of determining
which pin's hash value would be used for the hash value of all the
pins. Because equivalent cells in the two netlists may have pins in
different order, it was possible that they might end up with
different hashes. This was solved simply by always taking the
larger hash value of the two pins belonging to the permutable pair.
Now permutation works correctly for arbitrary subcircuits.
(Previously it worked for low-level components like MOSFETs because
the pin order is always the same.)
forced flattening to be done whenever any pin mismatch occurred,
which undermined the whole proxy pin method. With the proxy pins
fixed, reinstated the method of avoiding flattening when pin
issues can be trivially corrected. Also: Added output to the
pin matching for one mismatch case that was being missed.
decided that it is beneficial to break symmetries by net name;
it's just that net names should not be used before all symmetries
related to pins have been broken. So I rewrote the compare
routine to take an argument allowing or disallowing net name
matches, and make one call to break symmetries by pin name
followed by another call to break symmetries by net name. This
still solves the original problem, but does not allow symmetries
to be broken randomly on internal nets if names have been matched
in both netlists. Otherwise the output may report nets that
appear to be swapped, making the output confusing.
to check that the nodes with matching names are pins, but never does.
This results in an attempt to resolve automorphs by matching pin
names AND net names. However, net names can match without the nets
matching, as pointed out by Andrey Bondar (private communication).
Fixed simply by adding the specified check that the node being name-
matched is actually a pin.
formatted output to make it much cleaner and easier to read. This
is in preparation of correcting the circuit1<-->circuit2 asymmetry
in the MatchPins() routine.
the critical property (e.g., L for transistors) is required to
match exactly between devices in order to allow the additive
property (e.g., W for transistors) to be summed. The critical
property should match if all values are within the slop value,
for floating-point values. Note: The implementation is still
not rigorous, as the saved critical value may shift from
device to device; so comparing, e.g., 1.00 to 1.01 to 1.02 to
1.03, etc., can find that all individual comparisons are within
the slop value even though the slop is exceeded across all values.
ditch effort of matching based on combining devices with the same
critical property (e.g., adding gate widths together for transistors
of the same gate length, if the property records remain stubbornly
mismatched to the end). Thanks to Bondar Andrey Renatovich for
surfacing this issue and providing a reproducible example.
a long time ago into the code. The improvements collided with
intervening changes to the same routines and would not merge
cleanly, which is why they were never merged. Step 1: Show the
net name of a matching net that is missing a pin. Remove output
of missing pins that is redundant (pin names being output twice).
some errors failing to list in the output while also being responsible
for a number of non-errors showing up in the output. This fix may
substantially clean up netgen output. Also: Added text to the
output noting that pin matching may be incorrect with respect to
symmetries if the nets have failed to match.
port-to-port short (formed by "assign" in verilog or zero-valued
resistors in SPICE) does not get checked when counting nodes
before adding a proxy pin to a subcircuit in that cell, causing
the proxy pin to be assigned the same node number and forming an
unintended connection to the port-to-port connecting net.
to 1 before the loop over devices in "run", resulting in "M"
taking the value of the previous property record if the following
record did not have an "M" value, instead of setting it to 1.
PropertyMatch() but not corrected symmetrically between circuit1
and circuit2; this left the possibility that "M=1" in one
circuit vs. no "M" entry in the other would still pop up as a
property error, depending on which circuit (layout or schematic)
was listed first.
while back, shorted pins were moved into contiguous positions.
When that method was discovered to cause matching issues, it was
abandoned with a note that doing so might have unintended
consequences because other code might depend on the shorted pins
being contiguous. Such a case was just found, and corrected.
However, it was also found that shorted pins were still not
completely handled correctly in MatchPins(); a solution was
found that adds such pins to the "permutes" list (which needs to
be done if the shorted pins are to be correctly handled in any
higher level of the hierarchy, if there is one), and the
"permutes" list is then checked by MatchPins() to determine if
pins match because they belong to the same group of shorted
pins.
were not compared for sorting in the same way they are compared
for property matching. The "slop" value was treated as absolute,
not a percentage, so for example a slop of 0.01 on a dimension
of microns would cause all dimensions to be treated as round-off
error, and no sorting would occur.
before its component cells, and the component cells are read in as
SPICE netlists. Then the original verilog cell and its instances
need to have pins reordered to match the subcircuit definition in
the SPICE netlist. Otherwise, when verilog and SPICE netlists are
mixed, the order in which the files are read is critical, and
failures due to reading out-of-order are very obscure and nearly
impossible to debug.
the following: (1) Checking that the parent cell is verilog,
(2) only running after the two cells themselves have been compared
and matched, then (3) added the missing pin or pins while reordering
pins on instances (note: this may not work if the verilog netlist is
the first passed to netgen; that case needs to be checked).
(1) When a comment line follows a ".subckt" line, and the comment
line is empty or all whitespace, then the following line would
be ignored. This condition appears to be very specific and
was solved simply by detecting it and handling it.
(2) Occasionally the "M" parameter of a subcircuit will be recorded
as type double, and this was not being anticipated by the code
that checks if "M=1" matches a corresponding entry with no "M"
parameter. Simple fix to check the condition where the "M"
parameter is type double.
move to the start index before relinking the sorted entries. That
will cause properties to be lost whenever the start index is greater
than zero. Not sure why this hasn't been caught previously, or
whether other errors are involved here.
the removal of zero-valued devices between ports on the top level
(from version 254 they are ignored for levels under the top to
prevent port order from getting scrambled). An invalid check was
being made to determine if the cells being compared were the top
of the compare queue. This has been fixed.
string vs. integer) will cause a segfault. Not sure if
type promotion is needed at that point because the failing case
was a syntax error that caused a double value to be interpreted
as a string because it could not be cast into a numeric form.
when they are shorted, because doing so is scrambling the pin
order of cells with respect to the instance calls to the cell.
Not sure if there is any code that relies on shorted pins being
adjacent, though.
tracks the output printed to stdout when matching pins. One section
of this subroutine used the wrong pointers when writing to the Tcl
list (for eventual JSON output) which was the fundamental error.
Beyond that, the "debug" case (if used) would fail to run some of
the matching code, and the "no matching pin" case needed to be
handled for the Tcl list output. Now the terminal output, terminal
debug output, and Tcl list output should all be in agreement on the
pin lists.
connected only to ports and not to any devices, then they do not
show up in NodeClasses() and so pass through most of the checks
in MatchPins(). A separate correspondence check is needed to make
sure that the same shorted ports appear in both netlists.
to have unique class hashes. This has the problem that it prevents
comparing N-to-1 cells because declaring X->X1 as equivalent breaks
the original name equivalence of X->X. The new implementation adds
the switch "-unique" to preserve the original behavior. Otherwise,
the class hashes are made the same as the 2nd cell passed to the
command, and it is the responsibility of the person running LVS to
ensure that this is done in the correct direction.
network parallel/series networks. Instead, added a global option
with command "property tolerance strict|relaxed" to reinstate the
original (strict) behavior on demand, while relaxing it by default.
This allows certain series/parallel networks to match numerically
even though the schematic netlist may have combined individual
devices.
the parallel sorting routine. This fixes occasional property
errors with series-connected devices such as resistors. (2) Added
a method to associate properties with specific pins when pins are
permutable. This allows netgen to properly check a value like
source/drain area when the definition of source and drain has
changed due to permutation of the device. (3) Added a "property"
command extension "associate" to associate a property with a pin,
for use with the method described in (2).
LVS result. The property matching was failing to match (M=1) to
(M!=1) if M was not registered as a property name (which it often
isn't). This would allow devices with different numbers of
instances in parallel to be put in the same matching group,
which then could later identify as a mismatch if the instances
were checked in a different order.
netgen is supposed to be checking properties for symmetry sorting,
but not reporting anything. This causes mysterious property
mismatch errors that don't actually exist to show up in the
output.
underlying issue (which needs to be investigated), but it does
prevent netgen from crashing when it encounters it (netgen will
generate an erro message instead).
significant overhaul of the MatchPins() code, and better handles
issues with pins disconnected from nets and removes cases in
which proxy pins are incorrectly generated.
request #59 ("Pin match"). Because the pull request has rather
sweeping modifications, I am doing this in two steps. The change
that most breaks with existing comparison methods is in the
PinMatch() routine in netcmp.c, where the method of generating
proxy pins has been removed. There are specific cases for which
the proxy pin method exists, although these were coping with
issues arising from extraction in magic which have been dealt
with to some extend. Possibly the proxy pin method is no longer
needed. So the PinMatch() changes will be done in a second
commit where it's easier to revert or modify the changes without
affecting the modifications from this commit.
were implicit in the first instances but made explicit in a later
one. If more than one such implicit pin was handled for the same
cell, then the pin count would become wrong and rather unpredictable
behavior results.
to a single net (as can be done with assignments in verilog or with
zero-voltage sources or zero-value resistors in SPICE). Corrected
an error in the SPICE netlist reader that prevented the proper use
of zero-voltage sources as net splitters.
delimiter set when parsing pin names (the correct delimiter set
was used in one place but not in another). Extended the pin
matching to include the minor hack of ignoring the backslash
before backslash-escaped verilog names when there is otherwise
no exact match, since many tools convert verilog to SPICE by
removing the backslash and trailing space. This avoids pin
mismatches in a known set of use cases.
by Anton Blanchard, which prevents the double-loop in the
PropertyOptimize() routine from continuing the outer loop if
all devices in the run have already been merged.
summary, so that the summary lists the total number of devices as well
as the number of devices after parallel optimization, in the form
"device_name (M->N)", where "M" is the total number of devices, and
"N" is the number of devices after parallel combination. This makes
the output somewhat more meaningful to the end user. Implementation
as discussed in github issue #47.
should not be called after CreateTwoLists(). CreateTwoLists()
was being called in one case only to print the contents of the
cells, so that part was pulled out into a separate routine.
for each connection in the dump of incorrect nets. This is
definitely critical to finding local swapping errors, and needs
to be incorporated into the non-debug mode, preferably as part of
the JSON file dump. But that's for later.
Tim Edwards
Donn
D. Mitch Bailey