a "critical property". This lets a device define multiple critical
properties, all of which must match before additive properties can
be combined in the same device.
re-worked property command, "critical" properties must match
across devices so that all other properties can be combined as
specified (addition, parallel combination, or none). The code was
still based on the older notion of the "critical" property being
the one to add (and thus preventing multiple properties from being
added in different ways). This has now been fixed.
handle verilog syntax. Also: Added SPICE voltage and current
sources as separate classes (as opposed to being converted to
subcircuits, which was how they were previously handled). That
allowed voltage sources to be checked for zero value and removed
by shorting the ends together, as was being done for zero value
resistors (note that like zero-value resistors, removal is only
done if removing the component makes a better match than leaving
it in). In particular, yosys has SPICE netlist output that
converts equality assignments ("assign a = b") into zero-value
voltage sources, so these components need to be treated as
non-physical elements.
the possibility that a device (e.g., resistor or capacitor) may
not be a semiconductor device (in other words, a parasitic or
ideal device), and therefore uses "value" but not width and
length, and therefore "value" is a critical property to merge
both in series and parallel. Corrected the series/parallel
network optimization to prevent it from setting both M and S
records > 1 on the same device (which is ambiguous). To try
to get number of devices to match, where there are both series
and parallel devices, they will be merged across the critical
property early (before property matching).
accidentally erasing array delimiters from node names, a move that
surprisingly has no effect at all on LVS until the cell containing
the truncated nodes is flattened, at which point it causes odd and
confusing behavior that seems to have nothing to do with node names
at all.
in verilog net names, which are apparently legal in verilog but not
in python strings (if not escaped). This is somewhat critical for
running the LVS GUI as yosys can generate backslashes in generated
net names in the synthesized netlist.
type double before sorting (previously, property promotion was
being done after parallel sorting). Also, modified the verilog
file reading so that parameters and definitions that are numeric
are stored as numeric (not string) properties.
perfect). Given the complexities of the verilog language, the simple
strtok() tokenizer used by the SPICE parser is not sufficient. Wrote
a better tokenizer that can distinguish between whitespace and
functional tokens like parentheses, semicolons, etc., which are tokens
themselves but also token separators.
determine if a parameter is a floating-point number, integer, or
string, and set the parameter accordingly. Found an error in the
parameter comparison if the subcircuit definitions don't agree
on the type of parameter. Now all values are promoted to a single
type based on preference order (double, integer, string). Tested
on a verilog file with a primitive device type defined as a module
with its properties encoded as parameters. This successfully
matched against the SPICE primitive device.
Tim Edwards
Tim Edwards