to include type CLASS_MODULE in the list of types to descend into,
since "module" (black-box) types need to be checked for pin
matching even if they have no contents. This allows two verilog
netlists to be compared against each other.
definitions: Now correctly parses everything from the definition
name to the end of line as the definition value. Also: The
search for definitions in the body of the text does not reject
non-alphanumerics "_" and "$" in the definition name, without
which definition names containing those characters will go
unrecongized. Have not yet extended this to multi-line definition
values.
of the root name of the LHS net, and so would use the last root
name copied, which might have belonged to something entirely
different, or nothing at all.
are matched on circuits that have no elements. This condition
does not necessarily indicate an error, and matching pins has no
adverse affect (while refusing to match them certainly can).
scan structure because it is used in two different places and
would have to run a cost-prohibitive search of the cell's
object list. Also, was missing recording a bus input/output
signal from an "input" or "output" statement (as opposed to
in-line signals in the I/O list).
to bus pins over an array of instances. Takes care of the three
situations where the length of the signal bus equals the number of
instances; where the length of the signal bus is a multiple of
the number of instances; and where the number of instances is a
multiple of the length of the signal bus.
from 200 to 1024. Probably this should be dynamically allocated
and expanded as needed, as it is holding names that are of
increasing length as a hierarchy is descended and the instance
prefixes appended to the name.
However, I have identified an issue that has not yet been resolved,
which is that there can be automorphisms that are potentially
broken by property matching. Currently, the automorphisms are
arbitrarily resolved, then properties are matched---and may fail
accordingly.
in an "include" statement in either SPICE or verilog. Modified pin
matching behavior to force cells in both netlists to be marked as
black-box entries if either one is marked as a black-box entry (this
may not be needed, but shouldn't do any harm, either).
be removed because they do not match pins on the other cell being
compared, are marked with a different number (-2) than the usual
(-1). CleanupPins then only removes those pins that are marked,
rather than all disconnected pins.
a different way of treating "black box" cells. Even when the
"-blackbox" option is specified, any cell that has no definition
will be treated as a black box. This allows comparison of a
black-box netlist against a non-black-box netlist, such as a
verilog netlist vs. a SPICE netlist, without forcing the black-box
attribute on the SPICE netlist. Then, if the SPICE netlist
contains cells without elements such as fill/decap/tap cells,
they can be flattened and removed instead of forcing an error or
requiring the use of "ignore".
<col2_width>" to set the output format width, to avoid the fixed column
widths of 41 characters which can truncate long strings in the output
such as deep cell hierarchies. This command can be placed in the setup
script to widen the output columns to accomodate the result (to-do:
provide an "auto" mode to automatically determine the best width).
"prefix" with the specified path during install, so that netgen can
be installed in a separate location to be migrated to the final
install location, without appending the entire install path to
DESTDIR.
they are converted to the double-backslash escape that is the proper
JSON syntax for backslashes, instead of being removed, which changes
the name and can be confusing.
with increment/decrement syntax at the end. Also the parser now
handles additional keywords associated with behavioral verilog
(initial, specify) and flags modules with them as black-box entries.
that affects vectors sliced across instance arrays. Can cause vector
numbers to be out-of-bounds if an instance is arrayed but each
instance is listed separately.
inline-I/O syntax with "wire" (e.g., "input wire [3:0] test")
and addressed the failure to add buses declared in inline I/O
to the list of known buses.
verilog parser. The parser should now be able to handle any
conditionals anywhere in the verilog code. Also a bug was found
in the code that handles "a = b" assignments, and corrected.
code using the backtick expression. Also expanded the parsing of
"ifdef", "ifndef", and "endif" to include "elsif" and "else". All
forms of "if" statements should now be handled, since verilog does
not define boolean expressions in ifdef operators like most languages
do.
SPICE and verilog, in spite of the syntactical differences, to
account for the trick that qflow uses to replace the trailing space
in a verilog backslash-escaped name with a second backslash to get
a SPICE-compatible name that can be easily converted back to its
original verilog name without loss of information. What this means
is that verilog can read SPICE files containing verilog names (which
is illegal SPICE) and verilog files containing hacked-backslash
names (which is illegal verilog). This should be mostly harmless
although the wisdom of it is surely questionable.
assignment statements in verilog netlists, including assignment of
signal bundles. Also corrected handling of signal bundles in pin
connections, which had been corrected in qflow's verilog parser but
not copied back to netgen. Note that the syntax for signals multiplied
N times is still not handled.
Tim Edwards
Roman-Parise