second one of them, which is a failure to change CurrentTail when
an extra (implicit) pin was added to the last component in the
current cell, resulting in the failure of Node() to add the new
no-connect node, which instead overwrites the pin just created.
were implicit in the first instances but made explicit in a later
one. If more than one such implicit pin was handled for the same
cell, then the pin count would become wrong and rather unpredictable
behavior results.
even when the opposing netlist has a black-box entry for the same
cell. The black-box entry can't be flattened, so this just
results in the cell mysteriously disappearing from one side.
to a single net (as can be done with assignments in verilog or with
zero-voltage sources or zero-value resistors in SPICE). Corrected
an error in the SPICE netlist reader that prevented the proper use
of zero-voltage sources as net splitters.
delimiter set when parsing pin names (the correct delimiter set
was used in one place but not in another). Extended the pin
matching to include the minor hack of ignoring the backslash
before backslash-escaped verilog names when there is otherwise
no exact match, since many tools convert verilog to SPICE by
removing the backslash and trailing space. This avoids pin
mismatches in a known set of use cases.
definitions are handled correctly. Also: Added code to evaluate
simple expressions for array bounds. Previously the parser could
handle a value followed by "+" or "-" and a constant. Now it can
handle all basic arithmetic.
by Anton Blanchard, which prevents the double-loop in the
PropertyOptimize() routine from continuing the outer loop if
all devices in the run have already been merged.
summary, so that the summary lists the total number of devices as well
as the number of devices after parallel optimization, in the form
"device_name (M->N)", where "M" is the total number of devices, and
"N" is the number of devices after parallel combination. This makes
the output somewhat more meaningful to the end user. Implementation
as discussed in github issue #47.
parallel devices are prepended rather than appended, which avoids
having to search for the end of what may be a rapidly increasing
linked list of properties. This reduces the amount of time spent
in the parallel combination code. Thanks to Anton Blanchard for
pointing out this inefficiency.
speed up the time needed to flatten an instance, and add clarity to the
output by specifying the file number for each cell name being modified
during the pre-match stage.
ended up in the repository, as pointed out by Mitch Bailey in github
issue #44. Added lvs_manager.py to .gitignore to prevent that from
happening again in the future.
marked as unneeded, so I simply removed the code rather than
debug the issue, which was that buses got the delimeters erased
for checking but never put back again. Also: Modified the verilog
reading code so that if an empty set "()" is given for a pin, then
the initial proxy, which is a single net with the name prefix
"_noconnect_", can be promoted to a bus if further processing
reveals it to be a bus and not a single-bit signal.
used when ob may be NULL. Added a check in front for ob == NULL.
Also: Changed the disconnected node alert so that it does not
mention nodes marked "port_mismatch_error". These are disconnected
by definition, will show up in the pin list, and printing them as
"disconnected pins" is just confusing to the end user.
should not be called after CreateTwoLists(). CreateTwoLists()
was being called in one case only to print the contents of the
cells, so that part was pulled out into a separate routine.
routine does not have an exact equivalent in PrematchLists() and
needs to be run beforehand. This fix keeps FlattenUnmatched()
from being run on all cells at the beginning and restricts it
to being run on the contents of individual cells during matching,
after checking if either of the cells is a black-box. Avoiding
flattening contents of one side when the other is a black-box
(or simply doesn't contain any subcircuits or devices) prevents
unnecessary flattening of cells that will never get compared.
for each connection in the dump of incorrect nets. This is
definitely critical to finding local swapping errors, and needs
to be incorporated into the non-debug mode, preferably as part of
the JSON file dump. But that's for later.
contents (previously wasn't done), and also added sorting for items with
non-matching names which have only one item in the group for each circuit
(so they must be matching in some sense). This makes the output a bit
more readable without re-enabling the compute-intensive sorting method
for non-matching entries.
This fixes crash on macos due to wrong hash() being linked in.
It also makes sure that proper function defs are declared and available
(as required by C99) to make compile possible in newer compilers (e.g.
Apple clang) and to some extend prevent similar linkage issues happening
again.
Changed line breaks in log and stdout to better differentiate subcircuits.
Added merged series device counts and differentiated from parallel merged device counts.
Added file number to disconnected net, merged count messages.
Changed black box errors to show file numbers instead of hard coded values.
Final error cell list changed from all on one line to one per line.
Removed redundant display in black box warning.
print statement, and clarified the messages about non-matching
circuits at the end, all of them suggestions made by Mitch
Bailey (see issue #34 on github).
Tim Edwards
Kamyar Mohajerani
D. Mitch Bailey
Harald Pretl