Fischer Moseley 7dec6f513f examples: make verilog/amaranth versions of uart_logic_analyzer match		2024-10-07 20:51:03 -07:00
..
.gitignore	modify example design naming convention	2024-05-12 10:25:00 -07:00
build.sh	tests: include building examples in test suite	2024-10-07 20:50:15 -07:00
manta.yaml	examples: make verilog/amaranth versions of uart_logic_analyzer match	2024-10-07 20:51:03 -07:00
top_level.pcf	modify example design naming convention	2024-05-12 10:25:00 -07:00
top_level.sv	examples: make verilog/amaranth versions of uart_logic_analyzer match	2024-10-07 20:51:03 -07:00