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manta/examples/verilog/icestick
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Fischer Moseley 7dec6f513f examples: make verilog/amaranth versions of uart_logic_analyzer match 2024-10-07 20:51:03 -07:00
..
uart_io_core meta: sort imports with ruff 2024-10-07 20:51:03 -07:00
uart_logic_analyzer examples: make verilog/amaranth versions of uart_logic_analyzer match 2024-10-07 20:51:03 -07:00