132 lines
2.5 KiB
Systemverilog
132 lines
2.5 KiB
Systemverilog
`default_nettype none
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`timescale 1ns/1ps
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`define CP 10
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`define HCP 5
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module bridge_tx_tb;
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// https://www.youtube.com/watch?v=WCOAr-96bGc
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//boilerplate
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logic clk;
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logic rst;
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integer test_num;
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// uart_tx <--> tb signals
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logic txd;
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// uart_tx <--> bridge_tx signals
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logic [7:0] axid;
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logic axiv;
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logic axir;
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// bridge_tx <--> tb signals
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logic res_valid;
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logic res_ready;
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logic [15:0] res_data;
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uart_tx #(
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.DATA_WIDTH(8),
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.CLK_FREQ_HZ(100_000_000),
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.BAUDRATE(115200))
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uart_tx_uut (
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.clk(clk),
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.rst(rst),
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.txd(txd),
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.axiid(axid),
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.axiiv(axiv),
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.axiir(axir));
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bridge_tx bridge_tx_uut(
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.clk(clk),
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.axiod(axid),
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.axiov(axiv),
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.axior(axir),
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.res_valid(res_valid),
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.res_ready(res_ready),
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.res_data(res_data));
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always begin
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#`HCP
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clk = !clk;
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end
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initial begin
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$dumpfile("bridge_tx.vcd");
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$dumpvars(0, bridge_tx_tb);
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// setup and reset
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clk = 0;
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rst = 0;
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test_num = 0;
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res_valid = 0;
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res_data = 0;
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#`CP
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rst = 1;
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#`CP
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rst = 0;
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#(10*`CP);
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/* ==== Test 1 Begin ==== */
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$display("\n=== test 1: receive 0x0123 for baseline functionality ===");
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test_num = 1;
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res_data = 16'h0123;
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res_valid = 1;
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#`CP;
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assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
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res_valid = 0;
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#(100000*`CP);
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/* ==== Test 1 End ==== */
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/* ==== Test 2 Begin ==== */
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$display("\n=== test 2: receive 0x4567 for baseline functionality ===");
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test_num = 2;
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res_data = 16'h4567;
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res_valid = 1;
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#`CP;
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assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
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res_valid = 0;
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#(100000*`CP);
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/* ==== Test 2 End ==== */
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/* ==== Test 3 Begin ==== */
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$display("\n=== test 3: receive 0x89AB for baseline functionality ===");
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test_num = 3;
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res_data = 16'h89AB;
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res_valid = 1;
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#`CP;
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assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
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res_valid = 0;
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#(100000*`CP);
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/* ==== Test 3 End ==== */
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/* ==== Test 4 Begin ==== */
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$display("\n=== test 4: receive 0xCDEF for baseline functionality ===");
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test_num = 4;
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res_data = 16'hCDEF;
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res_valid = 1;
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#`CP;
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assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
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res_valid = 0;
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#(100000*`CP);
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/* ==== Test 4 End ==== */
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$finish();
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end
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endmodule
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`default_nettype wire |