102 lines
1.5 KiB
Plaintext
102 lines
1.5 KiB
Plaintext
[*]
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[*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
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[*] Wed Mar 1 02:04:43 2023
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[*]
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[dumpfile] "/Users/fischerm/fpga/manta/bus.vcd"
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[dumpfile_mtime] "Wed Mar 1 02:00:40 2023"
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[dumpfile_size] 91134
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[savefile] "/Users/fischerm/fpga/manta/bus.gtkw"
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[timestart] 0
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[size] 1710 994
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[pos] -1 -1
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*-21.981709 8420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] bus_tb.
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[sst_width] 353
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[signals_width] 276
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[sst_expanded] 1
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[sst_vpaned_height] 296
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@28
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bus_tb.clk
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bus_tb.rst
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@420
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bus_tb.test_num
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@200
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-
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-
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-tb --> uart_rx
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@28
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bus_tb.tb_urx_rxd
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@200
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-
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-
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-uart_rx --> bridge_rx
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@820
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bus_tb.urx_brx_axid[7:0]
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@28
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bus_tb.urx_brx_axiv
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@22
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bus_tb.urx.bit_index[4:0]
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@200
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-
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-
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-bridge_rx --> mem_1
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@22
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bus_tb.brx_mem_1_addr[15:0]
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bus_tb.brx_mem_1_rdata[15:0]
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bus_tb.brx_mem_1_wdata[15:0]
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@28
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bus_tb.brx_mem_1_rw
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bus_tb.brx_mem_1_valid
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@200
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-
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-
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-mem_1 --> mem_2
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@22
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bus_tb.mem_1_mem_2_addr[15:0]
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bus_tb.mem_1_mem_2_rdata[15:0]
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bus_tb.mem_1_mem_2_wdata[15:0]
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@28
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bus_tb.mem_1_mem_2_rw
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bus_tb.mem_1_mem_2_valid
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@200
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-
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-
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-mem_2 --> mem_3
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@22
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bus_tb.mem_2_mem_3_addr[15:0]
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bus_tb.mem_2_mem_3_rdata[15:0]
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@28
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bus_tb.mem_2_mem_3_rw
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bus_tb.mem_2_mem_3_valid
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@22
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bus_tb.mem_2_mem_3_wdata[15:0]
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@200
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-
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-
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-mem_3 --> bridge_tx
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@22
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bus_tb.mem_3_btx_addr[15:0]
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bus_tb.mem_3_btx_rdata[15:0]
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@28
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bus_tb.mem_3_btx_rw
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bus_tb.mem_3_btx_valid
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@22
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bus_tb.mem_3_btx_wdata[15:0]
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@200
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-
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-
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-bridge_tx --> uart_tx
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@23
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bus_tb.btx_utx_axid[7:0]
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@28
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bus_tb.btx_utx_axir
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bus_tb.btx_utx_axiv
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@200
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-
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-
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-uart_tx --> tb
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@28
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bus_tb.utx_tb_txd
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[pattern_trace] 1
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[pattern_trace] 0
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