19 lines
653 B
Markdown
19 lines
653 B
Markdown
# Roadmap
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## Prior to v1.0.0 release:
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_targeting August 2023_
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- Clean up UART testbenches, make them actually test things
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- Pull text from thesis into documentation site
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- Update docs with API reference
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- Make super super sure everything works (need hardware for that)
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- Port logic analyzer examples to the icestick
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- __IO Core:__ Clock domain crossing, check that >16 bit probes work
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- __Logic Analyzer Core:__ CDC, trigger modes, external trigger
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## Prior to v1.1.0 release:
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- Fix Ethernet packet format
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- Switch from Scapy to Python sockets library
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## Prior to v1.2.0 release:
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- [FuseSoC](https://github.com/fusesoc/fusesoc.github.io) Integration |