2023-07-20 04:27:12 +02:00
|
|
|
# Roadmap
|
|
|
|
|
|
|
|
|
|
## Prior to v1.0.0 release:
|
|
|
|
|
_targeting August 2023_
|
2023-07-24 18:03:46 +02:00
|
|
|
|
2023-07-20 04:27:12 +02:00
|
|
|
- Clean up UART testbenches, make them actually test things
|
|
|
|
|
- Pull text from thesis into documentation site
|
|
|
|
|
- Update docs with API reference
|
|
|
|
|
- Make super super sure everything works (need hardware for that)
|
|
|
|
|
- Port logic analyzer examples to the icestick
|
2023-07-24 18:03:46 +02:00
|
|
|
- __IO Core:__ Clock domain crossing, check that >16 bit probes work
|
2023-07-20 04:27:12 +02:00
|
|
|
- __Logic Analyzer Core:__ CDC, trigger modes, external trigger
|
|
|
|
|
|
|
|
|
|
## Prior to v1.1.0 release:
|
|
|
|
|
- Fix Ethernet packet format
|
|
|
|
|
- Switch from Scapy to Python sockets library
|
|
|
|
|
|
|
|
|
|
## Prior to v1.2.0 release:
|
|
|
|
|
- [FuseSoC](https://github.com/fusesoc/fusesoc.github.io) Integration
|
