manta/examples/verilog/icestick/uart_logic_analyzer
Fischer Moseley 470244966d gitignore: tidy and remove unnecessary per-directory gitignores 2026-02-25 15:02:15 -07:00
..
build.sh examples: use symlinked bash and Tcl scripts 2026-02-25 15:02:15 -07:00
manta.yaml uart: fix #36, explicitly handle scientific notation in YAML config 2025-04-06 18:28:29 -06:00
top_level.pcf modify example design naming convention 2024-05-12 10:25:00 -07:00
top_level.sv meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00