manta/doc/todo.md

ToDo

Deadlines

• 04/12 - BRAM Core
• 04/13 - Logic Analyzer working with >16 bit inputs. Currently held up by the sample memory, but will be resolved once BRAM core is ruggedized.
• 04/14 - CDC in the Logic Analyzer. Should be handled automatically, but just need to test it - probably with a SD card example.
• 04/15 - fischer's day off
• 04/16 - VCD export and .mem export for hardware-in-the-loop

release to PyPI lists - manta v0.0.1 out

• 04/17 - write logic analyzer lab

• 04/18 - beta tester round 2, run logic analyzer lab. ethernet tx if there's time

• 04/19 - Ethernet TX

• 04/20 - Ethernet TX

• 04/21 - Ethernet TX

• 04/22 - fischer's day off

• 04/23 - fischer's day off

• 04/28/23 - start writing docs site, move appropriate bits into thesis

• 05/05/23 - slack week

• 05/12/23 - thesis due

• 05/19/23 - thesis actually due

IO Core

• clock domain crossing
• add logic for ports >16 bits in width

Logic Analyzer Core

• clock domain crossing
• trigger modes
• external trigger

Meta

• consider making manta pass verilator lint - or at least as much of it as possible
• opencores listing
• fusesoc
• port more examples to the icestorm FPGA
• hardware-in-the-loop testing?