Fischer Moseley 28f40f2b7b add working l2 send in hardware

2023-04-28 14:57:36 -04:00

..

assets

update tutorial_1

2023-04-18 13:55:40 -04:00

javascripts

add docs and add trigger config for logic analyzer

2023-04-17 18:14:31 -04:00

stylesheets

one more docs update

2023-03-14 16:24:56 -04:00

block_memory_core.md

add docs and add trigger config for logic analyzer

2023-04-17 18:14:31 -04:00

index.md

update design philosphy in docs

2023-04-12 11:55:53 -04:00

installation.md

update tutorial_1

2023-04-18 13:55:40 -04:00

io_core.md

add a little info on the io cores

2023-03-14 16:24:56 -04:00

logic_analyzer_core.md

add working l2 send in hardware

2023-04-28 14:57:36 -04:00

lut_memory_core.md

add docs and add trigger config for logic analyzer

2023-04-17 18:14:31 -04:00

system_architecture.md

modify sim and generator, seems to work in simulation

2023-04-17 18:14:31 -04:00

todo.md

refactor logic analyzer a little, add ps2_decoder example, and implement trigger_loc

2023-04-18 01:06:39 -04:00

tools_used.md

add bus read/write to python

2023-03-17 19:04:59 -04:00

tutorial_0.md

import tutorial from yesterday, add mostly working bram core

2023-04-12 11:47:50 -04:00

tutorial_1.md

update tutorial_1

2023-04-18 13:55:40 -04:00

tutorial_2.md

initial commit tutorial 2

2023-04-18 12:42:39 -04:00