manta/test/functional_sim at 5ceefc8da9b57c9688a2a047afa976cbc3f6f17a - manta - Gitea: Git with a cup of tea

luke/manta

mirror of https://github.com/fischermoseley/manta.git synced 2026-09-02 02:38:27 +02:00

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Fischer Moseley 5ceefc8da9 this bram core has taken my soul

2023-04-12 18:15:50 -04:00

..

remove all narly verilog from python! 🤠

2023-04-08 16:23:02 -04:00

block_memory_tb

this bram core has taken my soul

2023-04-12 18:15:50 -04:00

update makefile to represent new functional sim locations

2023-04-09 22:33:58 -04:00

logic_analyzer_tb

remove all narly verilog from python! 🤠

2023-04-08 16:23:02 -04:00

bridge_rx_tb.sv

clean up inferred BRAM, trim whitespace

2023-04-03 21:20:58 -04:00

bridge_tx_tb.sv

clean up inferred BRAM, trim whitespace

2023-04-03 21:20:58 -04:00

bus_fix_tb.sv

clean up inferred BRAM, trim whitespace

2023-04-03 21:20:58 -04:00

lut_ram_tb.sv

clean up inferred BRAM, trim whitespace

2023-04-03 21:20:58 -04:00

uart_tb.sv

refactor test structure

2023-04-02 20:33:50 -04:00

uart_tx_tb.sv

clean up inferred BRAM, trim whitespace

2023-04-03 21:20:58 -04:00