manta/examples/verilog/nexys4_ddr
Fischer Moseley 9ac3181502 examples: fix typos 2024-11-07 09:50:55 -07:00
..
ether_logic_analyzer_io_core examples: fix typos 2024-11-07 09:50:55 -07:00
uart_host_to_fpga_mem tests: include building examples in test suite 2024-10-08 11:42:10 -06:00
uart_io_core meta: sort imports with ruff 2024-10-08 11:42:10 -06:00
uart_logic_analyzer logic_analyzer: only set triggers if extra info provided in config 2024-10-08 11:42:10 -06:00