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manta/examples/verilog/nexys4_ddr
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Fischer Moseley 9611c0b554 uart: fix #36, explicitly handle scientific notation in YAML config 2025-04-06 18:28:29 -06:00
..
ether_logic_analyzer_io_core meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
uart_host_to_fpga_mem uart: fix #36, explicitly handle scientific notation in YAML config 2025-04-06 18:28:29 -06:00
uart_io_core uart: fix #36, explicitly handle scientific notation in YAML config 2025-04-06 18:28:29 -06:00
uart_logic_analyzer uart: fix #36, explicitly handle scientific notation in YAML config 2025-04-06 18:28:29 -06:00