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manta/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem
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Fischer Moseley 9611c0b554 uart: fix #36, explicitly handle scientific notation in YAML config 2025-04-06 18:28:29 -06:00
..
.gitignore meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
build.sh meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
build.tcl rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
manta.yaml uart: fix #36, explicitly handle scientific notation in YAML config 2025-04-06 18:28:29 -06:00
top_level.sv meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
top_level.xdc meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
write.py manta: fix code generation from config file, update tests 2024-10-08 11:42:10 -06:00