From df2dbf4ec6da3b4c5f80a962a81605dbe795b6a7 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Fri, 28 Apr 2023 14:54:20 -0400
Subject: [PATCH] update makefile to reflect new paths

---
 Makefile                                            | 13 +++----------
 .../logic_analyzer_tb/logic_analyzer_tb.sv          |  4 ++--
 2 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/Makefile b/Makefile
index 61c8763..2397732 100644
--- a/Makefile
+++ b/Makefile
@@ -32,7 +32,7 @@ auto_gen:
 	python3 test/auto_gen/run_tests.py
 
 # Functional Simulation
-functional_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb lut_mem_tb
+functional_sim: io_core_tb logic_analyzer_tb bridge_rx_tb bridge_tx_tb lut_mem_tb
 
 ethernet_tx_tb:
 	iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_tx_tb.sv
@@ -68,20 +68,13 @@ logic_analyzer_tb:
 	vvp sim.out; 												\
 	rm sim.out
 
-bit_fifo_tb:
-	iverilog -g2012 -o sim.out -y src/manta 		\
-	test/functional_sim/bit_fifo_tb/bit_fifo_tb.sv 	\
-	test/functional_sim/bit_fifo_tb/bit_fifo.v
-	vvp sim.out
-	rm sim.out
-
 bridge_rx_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bridge_rx_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_rx_tb.sv
 	vvp sim.out
 	rm sim.out
 
 bridge_tx_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bridge_tx_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_tx_tb.sv
 	vvp sim.out
 	rm sim.out
 
diff --git a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
index 7403caf..c0dee09 100644
--- a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
+++ b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
@@ -195,8 +195,8 @@ module logic_analyzer_tb;
         write_reg(la.trig_blk.BASE_ADDR + 1, 1, "larry_arg");
 
         $display(" -> requesting start");
-        write_reg(2, 1, "request_start");
-        write_reg(2, 0, "request_start");
+        write_reg(3, 1, "request_start");
+        write_reg(3, 0, "request_start");
         #`CP
 
         $display(" -> set larry = 1");