diff --git a/Makefile b/Makefile
index cd3f749..d95db6b 100644
--- a/Makefile
+++ b/Makefile
@@ -3,6 +3,7 @@ test:
 	python3 -m pytest --cov
 
 format:
+	python3 -m ruff check --select I --fix
 	python3 -m ruff format
 
 clean:
diff --git a/examples/amaranth/uart_io_core.py b/examples/amaranth/uart_io_core.py
index 624780d..69c7670 100644
--- a/examples/amaranth/uart_io_core.py
+++ b/examples/amaranth/uart_io_core.py
@@ -1,7 +1,8 @@
+from time import sleep
+
 from amaranth import *
 from amaranth.lib import io
 from manta import *
-from time import sleep
 
 
 class UARTIOCoreExample(Elaboratable):
diff --git a/examples/amaranth/uart_logic_analyzer.py b/examples/amaranth/uart_logic_analyzer.py
index 4627977..4065416 100644
--- a/examples/amaranth/uart_logic_analyzer.py
+++ b/examples/amaranth/uart_logic_analyzer.py
@@ -1,7 +1,8 @@
+from time import sleep
+
 from amaranth import *
 from amaranth.lib import io
 from manta import *
-from time import sleep
 
 
 class UARTLogicAnalyzerExample(Elaboratable):
diff --git a/examples/verilog/icestick/uart_io_core/blinky.py b/examples/verilog/icestick/uart_io_core/blinky.py
index e66579e..f761db8 100644
--- a/examples/verilog/icestick/uart_io_core/blinky.py
+++ b/examples/verilog/icestick/uart_io_core/blinky.py
@@ -1,6 +1,7 @@
-from manta import *
 from time import sleep
 
+from manta import *
+
 manta = Manta.from_config("manta.yaml")
 
 i = 0
diff --git a/examples/verilog/nexys4_ddr/uart_io_core/blinky.py b/examples/verilog/nexys4_ddr/uart_io_core/blinky.py
index 1612555..06127f6 100644
--- a/examples/verilog/nexys4_ddr/uart_io_core/blinky.py
+++ b/examples/verilog/nexys4_ddr/uart_io_core/blinky.py
@@ -1,6 +1,7 @@
-from manta import *
-from time import sleep
 from random import randint
+from time import sleep
+
+from manta import *
 
 manta = Manta.from_config("manta.yaml")
 
diff --git a/src/manta/__init__.py b/src/manta/__init__.py
index a5e8034..fde3b6d 100644
--- a/src/manta/__init__.py
+++ b/src/manta/__init__.py
@@ -1,10 +1,10 @@
-from manta.manta import Manta
-from manta.uart import UARTInterface
-from manta.ethernet import EthernetInterface
-from manta.logic_analyzer import LogicAnalyzerCore, TriggerModes
-from manta.io_core import IOCore
-from manta.memory_core import MemoryCore
 from manta.cli import main
+from manta.ethernet import EthernetInterface
+from manta.io_core import IOCore
+from manta.logic_analyzer import LogicAnalyzerCore, TriggerModes
+from manta.manta import Manta
+from manta.memory_core import MemoryCore
+from manta.uart import UARTInterface
 
 __all__ = [
     "Manta",
diff --git a/src/manta/cli.py b/src/manta/cli.py
index 4d3148b..03bd879 100644
--- a/src/manta/cli.py
+++ b/src/manta/cli.py
@@ -1,8 +1,8 @@
+from importlib.metadata import distribution
+from sys import argv
+
 from manta.manta import Manta
 from manta.utils import *
-from sys import argv
-from importlib.metadata import distribution
-
 
 logo = f"""
                                         .
diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py
index 3cb82f2..8ee8b38 100644
--- a/src/manta/ethernet/__init__.py
+++ b/src/manta/ethernet/__init__.py
@@ -1,9 +1,11 @@
-from amaranth import *
-from manta.utils import *
-from manta.ethernet.source_bridge import UDPSourceBridge
-from manta.ethernet.sink_bridge import UDPSinkBridge
-from random import getrandbits
 import socket
+from random import getrandbits
+
+from amaranth import *
+
+from manta.ethernet.sink_bridge import UDPSinkBridge
+from manta.ethernet.source_bridge import UDPSourceBridge
+from manta.utils import *
 
 
 class EthernetInterface(Elaboratable):
diff --git a/src/manta/ethernet/liteeth_gen.py b/src/manta/ethernet/liteeth_gen.py
index 5ba0f22..220de47 100755
--- a/src/manta/ethernet/liteeth_gen.py
+++ b/src/manta/ethernet/liteeth_gen.py
@@ -37,31 +37,24 @@
 # Copyright (c) 2023 LumiGuide Fietsdetectie B.V. <goemansrowan@gmail.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
-from migen import *
-
-from litex.gen import *
-
-from litex.build.generic_platform import *
-from litex.build.xilinx.platform import XilinxPlatform
-from litex.build.lattice.platform import LatticePlatform
-
-from litex.soc.interconnect import wishbone
-from litex.soc.interconnect import axi
-from litex.soc.integration.soc_core import *
-from litex.soc.integration.builder import *
-from litex.soc.integration.soc import SoCRegion
-
-from liteeth.common import *
+from tempfile import TemporaryDirectory
 
 from liteeth import phy as liteeth_phys
-from liteeth.mac import LiteEthMAC
+from liteeth.common import *
 from liteeth.core import LiteEthUDPIPCore
 from liteeth.core.dhcp import LiteEthDHCP
-
-from liteeth.frontend.stream import LiteEthUDPStreamer
 from liteeth.frontend.etherbone import LiteEthEtherbone
-
-from tempfile import TemporaryDirectory
+from liteeth.frontend.stream import LiteEthUDPStreamer
+from liteeth.mac import LiteEthMAC
+from litex.build.generic_platform import *
+from litex.build.lattice.platform import LatticePlatform
+from litex.build.xilinx.platform import XilinxPlatform
+from litex.gen import *
+from litex.soc.integration.builder import *
+from litex.soc.integration.soc import SoCRegion
+from litex.soc.integration.soc_core import *
+from litex.soc.interconnect import axi, wishbone
+from migen import *
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -320,7 +313,7 @@ class PHYCore(SoCMini):
             if phy in [liteeth_phys.A7_1000BASEX, liteeth_phys.A7_2500BASEX]:
                 refclk_freq = core_config.get("refclk_freq", 0)
                 assert refclk_freq in [125e6, 156.25e6]
-                from liteeth.phy.a7_gtp import QPLLSettings, QPLL
+                from liteeth.phy.a7_gtp import QPLL, QPLLSettings
 
                 qpll_settings = QPLLSettings(
                     refclksel=0b001,
diff --git a/src/manta/ethernet/sink_bridge.py b/src/manta/ethernet/sink_bridge.py
index 621d8b9..27b065b 100644
--- a/src/manta/ethernet/sink_bridge.py
+++ b/src/manta/ethernet/sink_bridge.py
@@ -1,4 +1,5 @@
 from amaranth import *
+
 from manta.utils import *
 
 
diff --git a/src/manta/ethernet/source_bridge.py b/src/manta/ethernet/source_bridge.py
index 4ed8765..83c2127 100644
--- a/src/manta/ethernet/source_bridge.py
+++ b/src/manta/ethernet/source_bridge.py
@@ -1,4 +1,5 @@
 from amaranth import *
+
 from manta.utils import *
 
 
diff --git a/src/manta/io_core.py b/src/manta/io_core.py
index 19b36eb..9e3b925 100644
--- a/src/manta/io_core.py
+++ b/src/manta/io_core.py
@@ -1,7 +1,9 @@
-from amaranth import *
-from manta.utils import *
 from math import ceil
 
+from amaranth import *
+
+from manta.utils import *
+
 
 class IOCore(MantaCore):
     """
diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py
index 12371f3..64b1ec3 100644
--- a/src/manta/logic_analyzer/__init__.py
+++ b/src/manta/logic_analyzer/__init__.py
@@ -1,9 +1,10 @@
 from amaranth import *
-from manta.utils import *
-from manta.memory_core import MemoryCore
-from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock
-from manta.logic_analyzer.fsm import LogicAnalyzerFSM, TriggerModes
+
 from manta.logic_analyzer.capture import LogicAnalyzerCapture
+from manta.logic_analyzer.fsm import LogicAnalyzerFSM, TriggerModes
+from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock
+from manta.memory_core import MemoryCore
+from manta.utils import *
 
 import math
 
diff --git a/src/manta/logic_analyzer/capture.py b/src/manta/logic_analyzer/capture.py
index 49f773f..9d9c3a1 100644
--- a/src/manta/logic_analyzer/capture.py
+++ b/src/manta/logic_analyzer/capture.py
@@ -1,5 +1,5 @@
-from manta.logic_analyzer.playback import LogicAnalyzerPlayback
 from manta.logic_analyzer import TriggerModes
+from manta.logic_analyzer.playback import LogicAnalyzerPlayback
 
 
 class LogicAnalyzerCapture:
@@ -78,9 +78,10 @@ class LogicAnalyzerCapture:
         the core.
         """
 
-        from vcd import VCDWriter
         from datetime import datetime
 
+        from vcd import VCDWriter
+
         # Compute the timescale from the frequency of the provided clock
         half_period = 1 / (2 * self._interface._clock_freq)
         exponent = math.floor(math.log10(half_period))
diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py
index 7e4966a..9f1dcd7 100644
--- a/src/manta/logic_analyzer/fsm.py
+++ b/src/manta/logic_analyzer/fsm.py
@@ -1,5 +1,6 @@
 from amaranth import *
 from amaranth.lib.enum import IntEnum
+
 from manta.io_core import IOCore
 
 
diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py
index 48051d0..1c7d651 100644
--- a/src/manta/logic_analyzer/trigger_block.py
+++ b/src/manta/logic_analyzer/trigger_block.py
@@ -1,5 +1,6 @@
 from amaranth import *
 from amaranth.lib.enum import IntEnum
+
 from manta.io_core import IOCore
 
 
diff --git a/src/manta/manta.py b/src/manta/manta.py
index 75b791b..f8efaf7 100644
--- a/src/manta/manta.py
+++ b/src/manta/manta.py
@@ -1,11 +1,12 @@
+import yaml
 from amaranth import *
-from manta.uart import UARTInterface
+
 from manta.ethernet import EthernetInterface
 from manta.io_core import IOCore
-from manta.memory_core import MemoryCore
 from manta.logic_analyzer import LogicAnalyzerCore
+from manta.memory_core import MemoryCore
+from manta.uart import UARTInterface
 from manta.utils import *
-import yaml
 
 
 class Manta(Elaboratable):
diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py
index e9e86a3..055e312 100644
--- a/src/manta/memory_core.py
+++ b/src/manta/memory_core.py
@@ -1,8 +1,10 @@
-from amaranth import *
-from manta.utils import *
-from amaranth.lib.memory import Memory
 from math import ceil
 
+from amaranth import *
+from amaranth.lib.memory import Memory
+
+from manta.utils import *
+
 
 class MemoryCore(MantaCore):
     """
diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py
index fe48bbe..eb4dc77 100644
--- a/src/manta/uart/__init__.py
+++ b/src/manta/uart/__init__.py
@@ -1,11 +1,12 @@
 from amaranth import *
-from manta.utils import *
-from manta.uart.receiver import UARTReceiver
-from manta.uart.receive_bridge import ReceiveBridge
-from manta.uart.transmitter import UARTTransmitter
-from manta.uart.transmit_bridge import TransmitBridge
 from serial import Serial
 
+from manta.uart.receive_bridge import ReceiveBridge
+from manta.uart.receiver import UARTReceiver
+from manta.uart.transmit_bridge import TransmitBridge
+from manta.uart.transmitter import UARTTransmitter
+from manta.utils import *
+
 
 class UARTInterface(Elaboratable):
     """
@@ -127,7 +128,7 @@ class UARTInterface(Elaboratable):
 
         if ports[0].serial_number != ports[1].serial_number:
             raise ValueError(
-                f"Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices."
+                "Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices."
             )
 
         if ports[0].location > ports[1].location:
diff --git a/src/manta/uart/receive_bridge.py b/src/manta/uart/receive_bridge.py
index d78c4bd..f0b8187 100644
--- a/src/manta/uart/receive_bridge.py
+++ b/src/manta/uart/receive_bridge.py
@@ -1,6 +1,6 @@
 from amaranth import *
-from amaranth.lib.enum import IntEnum
 from amaranth.lib.data import ArrayLayout
+from amaranth.lib.enum import IntEnum
 
 
 class States(IntEnum):
diff --git a/src/manta/utils.py b/src/manta/utils.py
index eef0f8e..0cb891b 100644
--- a/src/manta/utils.py
+++ b/src/manta/utils.py
@@ -1,10 +1,11 @@
+import os
+from abc import ABC, abstractmethod
+from pathlib import Path
+from random import sample
+
 from amaranth import Elaboratable
 from amaranth.lib import data
 from amaranth.sim import Simulator
-from abc import ABC, abstractmethod
-from random import sample
-from pathlib import Path
-import os
 
 
 class MantaCore(ABC, Elaboratable):
diff --git a/test/test_bridge_rx_sim.py b/test/test_bridge_rx_sim.py
index bf08791..beb603e 100644
--- a/test/test_bridge_rx_sim.py
+++ b/test/test_bridge_rx_sim.py
@@ -1,7 +1,6 @@
 from manta.uart import ReceiveBridge
 from manta.utils import *
 
-
 bridge_rx = ReceiveBridge()
 
 
diff --git a/test/test_bridge_tx_sim.py b/test/test_bridge_tx_sim.py
index 029389f..b9429d8 100644
--- a/test/test_bridge_tx_sim.py
+++ b/test/test_bridge_tx_sim.py
@@ -1,7 +1,7 @@
-from manta.uart import TransmitBridge
-from manta.utils import *
 from random import sample
 
+from manta.uart import TransmitBridge
+from manta.utils import *
 
 bridge_tx = TransmitBridge()
 
diff --git a/test/test_config_export.py b/test/test_config_export.py
index 1234af5..743bf42 100644
--- a/test/test_config_export.py
+++ b/test/test_config_export.py
@@ -1,8 +1,8 @@
+import tempfile
+
+import yaml
 from amaranth import *
 from manta import *
-import tempfile
-import os
-import yaml
 
 
 def test_io_core_dump():
diff --git a/test/test_examples_build.py b/test/test_examples_build.py
index de4852f..74eb60a 100644
--- a/test/test_examples_build.py
+++ b/test/test_examples_build.py
@@ -1,7 +1,8 @@
-import subprocess
-import pytest
-import sys
 import os
+import subprocess
+import sys
+
+import pytest
 
 verilog_root_dirs = [
     "examples/verilog/icestick/uart_io_core",
@@ -28,14 +29,14 @@ parent_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
 sys.path.insert(0, parent_dir)
 
 # Import Examples
-from examples.amaranth.uart_io_core import UARTIOCoreExample
-from examples.amaranth.uart_logic_analyzer import UARTLogicAnalyzerExample
-from examples.amaranth.uart_memory_core import UARTMemoryCoreExample
-
 # Import Platforms
 from amaranth_boards.icestick import ICEStickPlatform
 from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 
+from examples.amaranth.uart_io_core import UARTIOCoreExample
+from examples.amaranth.uart_logic_analyzer import UARTLogicAnalyzerExample
+from examples.amaranth.uart_memory_core import UARTMemoryCoreExample
+
 # Manually specify a list of examples/platforms to test.
 
 # This is necessary as some examples don't work without some amount of onboard
diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py
index d6b1415..0ceb7df 100644
--- a/test/test_io_core_hw.py
+++ b/test/test_io_core_hw.py
@@ -1,12 +1,13 @@
+import os
+from random import getrandbits
+
+import pytest
 from amaranth import *
 from amaranth.lib import io
-from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from amaranth_boards.icestick import ICEStickPlatform
+from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from manta import *
 from manta.utils import *
-import pytest
-from random import getrandbits
-import os
 
 
 class IOCoreLoopbackTest(Elaboratable):
diff --git a/test/test_io_core_sim.py b/test/test_io_core_sim.py
index 31dbd6f..7dac277 100644
--- a/test/test_io_core_sim.py
+++ b/test/test_io_core_sim.py
@@ -1,7 +1,8 @@
+from random import getrandbits
+
 from amaranth import *
 from manta import *
 from manta.utils import *
-from random import getrandbits
 
 probe0 = Signal(1)
 probe1 = Signal(2)
diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py
index c1aa6e7..3b91092 100644
--- a/test/test_logic_analyzer_hw.py
+++ b/test/test_logic_analyzer_hw.py
@@ -1,11 +1,12 @@
+import os
+
+import pytest
 from amaranth import *
 from amaranth.lib import io
-from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from amaranth_boards.icestick import ICEStickPlatform
+from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from manta import *
 from manta.utils import *
-import pytest
-import os
 
 
 class LogicAnalyzerCounterTest(Elaboratable):
diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py
index 0d42569..aaf08e8 100644
--- a/test/test_logic_analyzer_sim.py
+++ b/test/test_logic_analyzer_sim.py
@@ -2,7 +2,6 @@ from amaranth import *
 from manta.logic_analyzer import LogicAnalyzerCore
 from manta.logic_analyzer.trigger_block import Operations
 from manta.utils import *
-from random import sample
 
 larry = Signal(1)
 curly = Signal(3)
diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py
index 075cd78..9cf31c7 100644
--- a/test/test_mem_core_hw.py
+++ b/test/test_mem_core_hw.py
@@ -1,13 +1,13 @@
+import os
+from random import getrandbits
+
+import pytest
 from amaranth import *
 from amaranth.lib import io
-from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from amaranth_boards.icestick import ICEStickPlatform
+from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from manta import *
 from manta.utils import *
-import pytest
-from random import getrandbits
-from math import ceil, log2
-import os
 
 
 class MemoryCoreLoopbackTest(Elaboratable):
diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py
index 7466002..6bf18b8 100644
--- a/test/test_mem_core_sim.py
+++ b/test/test_mem_core_sim.py
@@ -1,8 +1,9 @@
+from math import ceil
+from random import choice, getrandbits, randint
+
+import pytest
 from manta.memory_core import MemoryCore
 from manta.utils import *
-from random import randint, choice, getrandbits
-from math import ceil
-import pytest
 
 
 class MemoryCoreTests:
diff --git a/test/test_source_bridge_sim.py b/test/test_source_bridge_sim.py
index 04654ba..0e827c9 100644
--- a/test/test_source_bridge_sim.py
+++ b/test/test_source_bridge_sim.py
@@ -1,7 +1,6 @@
 from manta.ethernet import UDPSourceBridge
 from manta.utils import *
 
-
 source_bridge = UDPSourceBridge()
 
 
diff --git a/test/test_toolchains.py b/test/test_toolchains.py
index 1ddc98d..04dace5 100644
--- a/test/test_toolchains.py
+++ b/test/test_toolchains.py
@@ -1,8 +1,8 @@
-from amaranth_boards.test.blinky import *
-from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
-from amaranth_boards.icestick import ICEStickPlatform
-from manta.utils import *
 import pytest
+from amaranth_boards.icestick import ICEStickPlatform
+from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
+from amaranth_boards.test.blinky import *
+from manta.utils import *
 
 
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")
diff --git a/test/test_uart_rx_sim.py b/test/test_uart_rx_sim.py
index b2c7c9b..b6b3680 100644
--- a/test/test_uart_rx_sim.py
+++ b/test/test_uart_rx_sim.py
@@ -1,7 +1,6 @@
 from manta.uart import UARTReceiver
 from manta.utils import *
 
-
 uart_rx = UARTReceiver(clocks_per_baud=10)
 
 
diff --git a/test/test_uart_tx_sim.py b/test/test_uart_tx_sim.py
index 088df2d..7933a84 100644
--- a/test/test_uart_tx_sim.py
+++ b/test/test_uart_tx_sim.py
@@ -1,7 +1,6 @@
 from manta.uart import UARTTransmitter
 from manta.utils import *
 
-
 uart_tx = UARTTransmitter(clocks_per_baud=10)
 
 
diff --git a/test/test_verilog_gen.py b/test/test_verilog_gen.py
index 739f3bd..642841a 100644
--- a/test/test_verilog_gen.py
+++ b/test/test_verilog_gen.py
@@ -1,6 +1,7 @@
-from manta.cli import gen, inst
-import tempfile
 import os
+import tempfile
+
+from manta.cli import gen, inst
 
 
 def test_verilog_gen():