157 lines
4.3 KiB
Makefile
157 lines
4.3 KiB
Makefile
test: auto_gen sim formal
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examples: icestick nexys_a7
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clean:
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rm *.out *.vcd
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rm **/lab-bc.py
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rm -rf dist/
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rm -rf src/mantaray.egg-info
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rm -rf test/formal_verification/*_basic
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rm -rf test/formal_verification/*_cover
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rm -f examples/nexys_a7/*/obj/*
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rm -f examples/nexys_a7/*/src/manta.v
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rm -f examples/icestick/*/*.bin
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rm -f examples/icestick/*/manta.v
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serve_docs:
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mkdocs serve
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total_loc:
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find . -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.yml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
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real_loc:
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find src test -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
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# Python Operations
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python_build:
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python3 -m build
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pypi_upload: build
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python3 -m twine upload --repository testpypi dist/*
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python_lint:
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python3 -m black src/manta/__init__.py
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python3 -m black src/manta/__main__.py
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# API Generation Tests
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auto_gen:
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python3 test/auto_gen/run_tests.py
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# Functional Simulation
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sim: ethernet_tx_tb ethernet_rx_tb mac_tb block_memory_tb io_core_tb logic_analyzer_tb bridge_rx_tb bridge_tx_tb lut_mem_tb block_memory_tb
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ethernet_tx_tb:
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iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_tx_tb.sv
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vvp sim.out
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rm sim.out
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ethernet_rx_tb:
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iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_rx_tb.sv
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vvp sim.out
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rm sim.out
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mac_tb:
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iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/mac_tb.sv
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vvp sim.out
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rm sim.out
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block_memory_tb:
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iverilog -g2012 -o sim.out -y src/manta/block_mem_core test/functional_sim/block_memory_tb.sv
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vvp sim.out
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rm sim.out
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io_core_tb:
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iverilog -g2012 -o sim.out -y src/manta \
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test/functional_sim/io_core_tb/io_core_tb.sv \
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test/functional_sim/io_core_tb/io_core.v
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vvp sim.out
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rm sim.out
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logic_analyzer_tb:
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cd test/functional_sim/logic_analyzer_tb; \
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manta gen manta.yaml manta.v; \
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iverilog -g2012 -o sim.out logic_analyzer_tb.sv manta.v; \
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vvp sim.out; \
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rm sim.out
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bridge_rx_tb:
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iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_rx_tb.sv
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vvp sim.out
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rm sim.out
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bridge_tx_tb:
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iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_tx_tb.sv
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vvp sim.out
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rm sim.out
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lut_mem_tb:
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iverilog -g2012 -o sim.out -y src/manta/lut_mem_core test/functional_sim/lut_mem_tb.sv
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vvp sim.out
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rm sim.out
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# Formal Verification
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formal:
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sby -f test/formal_verification/uart_rx.sby
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sby -f test/formal_verification/bridge_rx.sby
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# Build Examples
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nexys_a7: nexys_a7_video_sprite_uart nexys_a7_io_core nexys_a7_ps2_logic_analyzer nexys_a7_lut_mem
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nexys_a7_io_core_ether:
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cd examples/nexys_a7/io_core_ether/;\
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manta gen manta.yaml manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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python3 lab-bc.py
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nexys_a7_io_core_uart:
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cd examples/nexys_a7/io_core_uart/; \
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manta gen manta.yaml manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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python3 lab-bc.py
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nexys_a7_lut_mem_ether:
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cd examples/nexys_a7/lut_mem_ether/;\
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manta gen manta.yaml manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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python3 lab-bc.py
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nexys_a7_lut_mem_uart:
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cd examples/nexys_a7/lut_mem_uart/;\
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manta gen manta.yaml manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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python3 lab-bc.py
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nexys_a7_ps2_logic_analyzer:
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cd examples/nexys_a7/ps2_logic_analyzer/; \
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manta gen manta.yaml src/manta.v; \
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manta playback manta.yaml my_logic_analyzer sim/playback.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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python3 lab-bc.py
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nexys_a7_video_sprite_ether:
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cd examples/nexys_a7/video_sprite_ether;\
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manta gen manta.yaml src/manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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python3 lab-bc.py
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nexys_a7_video_sprite_uart:
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cd examples/nexys_a7/video_sprite_uart; \
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manta gen manta.yaml src/manta.v; \
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wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
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python3 lab-bc.py
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icestick: icestick_io_core icestick_lut_mem
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icestick_io_core:
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cd examples/icestick/io_core/; \
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manta gen manta.yaml manta.v; \
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./build.sh
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icestick_lut_mem:
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cd examples/icestick/lut_mem/; \
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manta gen manta.yaml manta.v; \
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./build.sh
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