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slim down video_sprite example, ready for manta brams

This commit is contained in:
Fischer Moseley 2023-04-12 20:37:43 -04:00
parent 4ece833ea1
commit c1dcc7faa6
3 changed files with 49 additions and 1100 deletions
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1024
examples/nexys_a7/video_sprite/data/example.mem
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64
examples/nexys_a7/video_sprite/src/image_sprite.sv
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@ -1,64 +0,0 @@
`timescale 1ns / 1ps
`default_nettype none
`include "iverilog_hack.svh"
module image_sprite #(
parameter WIDTH=256, HEIGHT=256) (
input wire pixel_clk_in,
input wire rst_in,
input wire [10:0] x_in, hcount_in,
input wire [9:0] y_in, vcount_in,
output logic [11:0] pixel_out);
// calculate rom address
logic [$clog2(WIDTH*HEIGHT)-1:0] image_addr;
assign image_addr = (hcount_in - x_in) + ((vcount_in - y_in) * WIDTH);
logic in_sprite;
assign in_sprite = ((hcount_in >= x_in && hcount_in < (x_in + WIDTH)) &&
(vcount_in >= y_in && vcount_in < (y_in + HEIGHT)));
// image BRAM
xilinx_single_port_ram_read_first #(
.RAM_WIDTH(8),
.RAM_DEPTH(WIDTH*HEIGHT),
.RAM_PERFORMANCE("HIGH_PERFORMANCE"),
.INIT_FILE(`FPATH(image.mem))
) image_bram (
.addra(image_addr),
.dina(),
.clka(pixel_clk_in),
.wea(1'b0),
.ena(1'b1),
.rsta(1'b0),
.regcea(1'b1),
.douta(color_lookup)
);
// lookup
logic [7:0] color_lookup;
// pallete BRAM
xilinx_single_port_ram_read_first #(
.RAM_WIDTH(12),
.RAM_DEPTH(256),
.RAM_PERFORMANCE("HIGH_PERFORMANCE"),
.INIT_FILE(`FPATH(pallete.mem))
) pallete_bram (
.addra(color_lookup),
.dina(),
.clka(pixel_clk_in),
.wea(1'b0),
.ena(1'b1),
.rsta(1'b0),
.regcea(1'b1),
.douta(color)
);
logic [11:0] color;
assign pixel_out = in_sprite ? color : 0;
endmodule
`default_nettype none

61
examples/nexys_a7/video_sprite/src/top_level.sv
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@ -12,16 +12,16 @@ module top_level(
output logic vga_hs, vga_vs output logic vga_hs, vga_vs
); );
/* Video Pipeline */
logic clk_65mhz; logic clk_65mhz;
clk_wiz_lab3 clk_gen( clk_wiz_lab3 clk_gen(
.clk_in1(clk_100mhz), .clk_in1(clk_100mhz),
.clk_out1(clk_65mhz)); .clk_out1(clk_65mhz));
logic [10:0] hcount; // pixel on current line // VGA signals
logic [9:0] vcount; // line number logic [10:0] hcount;
logic hsync, vsync, blank; //control signals for vga logic [9:0] vcount;
logic hsync, vsync, blank;
vga vga_gen( vga vga_gen(
.pixel_clk_in(clk_65mhz), .pixel_clk_in(clk_65mhz),
@ -31,14 +31,51 @@ module top_level(
.vsync_out(vsync), .vsync_out(vsync),
.blank_out(blank)); .blank_out(blank));
image_sprite img_sprite ( localparam WIDTH = 256;
.pixel_clk_in(clk_65mhz), localparam HEIGHT = 256;
.rst_in(btnc),
.x_in(0), // calculate rom address
.hcount_in(hcount), logic [$clog2(WIDTH*HEIGHT)-1:0] image_addr;
.y_in(0), assign image_addr = (hcount_in - x_in) + ((vcount_in - y_in) * WIDTH);
.vcount_in(vcount),
.pixel_out(color)); logic in_sprite;
assign in_sprite = ((hcount_in >= x_in && hcount_in < (x_in + WIDTH)) &&
(vcount_in >= y_in && vcount_in < (y_in + HEIGHT)));
// image BRAM
xilinx_single_port_ram_read_first #(
.RAM_WIDTH(8),
.RAM_DEPTH(WIDTH*HEIGHT),
.RAM_PERFORMANCE("HIGH_PERFORMANCE"),
.INIT_FILE(`FPATH(image.mem))
) image_bram (
.addra(image_addr),
.dina(),
.clka(clk_65mhz),
.wea(1'b0),
.ena(1'b1),
.rsta(1'b0),
.regcea(1'b1),
.douta(color_lookup));
// lookup
logic [7:0] color_lookup;
// pallete BRAM
xilinx_single_port_ram_read_first #(
.RAM_WIDTH(12),
.RAM_DEPTH(256),
.RAM_PERFORMANCE("HIGH_PERFORMANCE"),
.INIT_FILE(`FPATH(palette.mem))
) pallete_bram (
.addra(color_lookup),
.dina(),
.clka(clk_65mhz),
.wea(1'b0),
.ena(1'b1),
.rsta(1'b0),
.regcea(1'b1),
.douta(color));
logic [11:0] color; logic [11:0] color;