From c1dcc7faa6a0f6bf9d564517c3942a26030553d9 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Wed, 12 Apr 2023 20:37:43 -0400
Subject: [PATCH] slim down video_sprite example, ready for manta brams

---
 .../nexys_a7/video_sprite/data/example.mem    | 1024 -----------------
 .../nexys_a7/video_sprite/src/image_sprite.sv |   64 --
 .../nexys_a7/video_sprite/src/top_level.sv    |   61 +-
 3 files changed, 49 insertions(+), 1100 deletions(-)
 delete mode 100644 examples/nexys_a7/video_sprite/data/example.mem
 delete mode 100644 examples/nexys_a7/video_sprite/src/image_sprite.sv

diff --git a/examples/nexys_a7/video_sprite/data/example.mem b/examples/nexys_a7/video_sprite/data/example.mem
deleted file mode 100644
index e66ab88..0000000
--- a/examples/nexys_a7/video_sprite/data/example.mem
+++ /dev/null
@@ -1,1024 +0,0 @@
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\ No newline at end of file
diff --git a/examples/nexys_a7/video_sprite/src/image_sprite.sv b/examples/nexys_a7/video_sprite/src/image_sprite.sv
deleted file mode 100644
index 0b2f8fb..0000000
--- a/examples/nexys_a7/video_sprite/src/image_sprite.sv
+++ /dev/null
@@ -1,64 +0,0 @@
-`timescale 1ns / 1ps
-`default_nettype none
-
-`include "iverilog_hack.svh"
-
-module image_sprite #(
-  parameter WIDTH=256, HEIGHT=256) (
-  input wire pixel_clk_in,
-  input wire rst_in,
-  input wire [10:0] x_in, hcount_in,
-  input wire [9:0]  y_in, vcount_in,
-  output logic [11:0] pixel_out);
-
-  // calculate rom address
-  logic [$clog2(WIDTH*HEIGHT)-1:0] image_addr;
-  assign image_addr = (hcount_in - x_in) + ((vcount_in - y_in) * WIDTH);
-
-  logic in_sprite;
-  assign in_sprite = ((hcount_in >= x_in && hcount_in < (x_in + WIDTH)) &&
-                      (vcount_in >= y_in && vcount_in < (y_in + HEIGHT)));
-
-  // image BRAM
-  xilinx_single_port_ram_read_first #(
-    .RAM_WIDTH(8),
-    .RAM_DEPTH(WIDTH*HEIGHT),
-    .RAM_PERFORMANCE("HIGH_PERFORMANCE"),
-    .INIT_FILE(`FPATH(image.mem))
-  ) image_bram (
-    .addra(image_addr),
-    .dina(),
-    .clka(pixel_clk_in),
-    .wea(1'b0),
-    .ena(1'b1),
-    .rsta(1'b0),
-    .regcea(1'b1),
-    .douta(color_lookup)
-    );
-
-  // lookup
-  logic [7:0] color_lookup;
-
-  // pallete BRAM
-  xilinx_single_port_ram_read_first #(
-    .RAM_WIDTH(12),
-    .RAM_DEPTH(256),
-    .RAM_PERFORMANCE("HIGH_PERFORMANCE"),
-    .INIT_FILE(`FPATH(pallete.mem))
-  ) pallete_bram (
-    .addra(color_lookup),
-    .dina(),
-    .clka(pixel_clk_in),
-    .wea(1'b0),
-    .ena(1'b1),
-    .rsta(1'b0),
-    .regcea(1'b1),
-    .douta(color)
-  );
-
-  logic [11:0] color;
-
-  assign pixel_out = in_sprite ? color : 0;
-endmodule
-
-`default_nettype none
diff --git a/examples/nexys_a7/video_sprite/src/top_level.sv b/examples/nexys_a7/video_sprite/src/top_level.sv
index 18ad33f..8f74683 100644
--- a/examples/nexys_a7/video_sprite/src/top_level.sv
+++ b/examples/nexys_a7/video_sprite/src/top_level.sv
@@ -12,16 +12,16 @@ module top_level(
   output logic vga_hs, vga_vs
   );
 
-  /* Video Pipeline */
   logic clk_65mhz;
 
   clk_wiz_lab3 clk_gen(
     .clk_in1(clk_100mhz),
     .clk_out1(clk_65mhz));
 
-  logic [10:0] hcount;    // pixel on current line
-  logic [9:0] vcount;     // line number
-  logic hsync, vsync, blank; //control signals for vga
+  // VGA signals
+  logic [10:0] hcount;
+  logic [9:0] vcount;
+  logic hsync, vsync, blank;
 
   vga vga_gen(
     .pixel_clk_in(clk_65mhz),
@@ -31,14 +31,51 @@ module top_level(
     .vsync_out(vsync),
     .blank_out(blank));
 
-  image_sprite img_sprite (
-    .pixel_clk_in(clk_65mhz),
-    .rst_in(btnc),
-    .x_in(0),
-    .hcount_in(hcount),
-    .y_in(0),
-    .vcount_in(vcount),
-    .pixel_out(color));
+  localparam WIDTH = 256;
+  localparam HEIGHT = 256;
+
+  // calculate rom address
+  logic [$clog2(WIDTH*HEIGHT)-1:0] image_addr;
+  assign image_addr = (hcount_in - x_in) + ((vcount_in - y_in) * WIDTH);
+
+  logic in_sprite;
+  assign in_sprite = ((hcount_in >= x_in && hcount_in < (x_in + WIDTH)) &&
+                      (vcount_in >= y_in && vcount_in < (y_in + HEIGHT)));
+
+  // image BRAM
+  xilinx_single_port_ram_read_first #(
+    .RAM_WIDTH(8),
+    .RAM_DEPTH(WIDTH*HEIGHT),
+    .RAM_PERFORMANCE("HIGH_PERFORMANCE"),
+    .INIT_FILE(`FPATH(image.mem))
+  ) image_bram (
+    .addra(image_addr),
+    .dina(),
+    .clka(clk_65mhz),
+    .wea(1'b0),
+    .ena(1'b1),
+    .rsta(1'b0),
+    .regcea(1'b1),
+    .douta(color_lookup));
+
+  // lookup
+  logic [7:0] color_lookup;
+
+  // pallete BRAM
+  xilinx_single_port_ram_read_first #(
+    .RAM_WIDTH(12),
+    .RAM_DEPTH(256),
+    .RAM_PERFORMANCE("HIGH_PERFORMANCE"),
+    .INIT_FILE(`FPATH(palette.mem))
+  ) pallete_bram (
+    .addra(color_lookup),
+    .dina(),
+    .clka(clk_65mhz),
+    .wea(1'b0),
+    .ena(1'b1),
+    .rsta(1'b0),
+    .regcea(1'b1),
+    .douta(color));
 
   logic [11:0] color;