65 lines
1.4 KiB
Systemverilog
65 lines
1.4 KiB
Systemverilog
`timescale 1ns / 1ps
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`default_nettype none
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`include "iverilog_hack.svh"
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module image_sprite #(
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parameter WIDTH=256, HEIGHT=256) (
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input wire pixel_clk_in,
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input wire rst_in,
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input wire [10:0] x_in, hcount_in,
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input wire [9:0] y_in, vcount_in,
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output logic [11:0] pixel_out);
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// calculate rom address
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logic [$clog2(WIDTH*HEIGHT)-1:0] image_addr;
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assign image_addr = (hcount_in - x_in) + ((vcount_in - y_in) * WIDTH);
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logic in_sprite;
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assign in_sprite = ((hcount_in >= x_in && hcount_in < (x_in + WIDTH)) &&
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(vcount_in >= y_in && vcount_in < (y_in + HEIGHT)));
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// image BRAM
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xilinx_single_port_ram_read_first #(
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.RAM_WIDTH(8),
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.RAM_DEPTH(WIDTH*HEIGHT),
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.RAM_PERFORMANCE("HIGH_PERFORMANCE"),
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.INIT_FILE(`FPATH(image.mem))
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) image_bram (
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.addra(image_addr),
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.dina(),
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.clka(pixel_clk_in),
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.wea(1'b0),
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.ena(1'b1),
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.rsta(1'b0),
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.regcea(1'b1),
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.douta(color_lookup)
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);
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// lookup
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logic [7:0] color_lookup;
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// pallete BRAM
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xilinx_single_port_ram_read_first #(
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.RAM_WIDTH(12),
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.RAM_DEPTH(256),
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.RAM_PERFORMANCE("HIGH_PERFORMANCE"),
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.INIT_FILE(`FPATH(pallete.mem))
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) pallete_bram (
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.addra(color_lookup),
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.dina(),
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.clka(pixel_clk_in),
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.wea(1'b0),
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.ena(1'b1),
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.rsta(1'b0),
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.regcea(1'b1),
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.douta(color)
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);
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logic [11:0] color;
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assign pixel_out = in_sprite ? color : 0;
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endmodule
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`default_nettype none
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