add signal to vcd export to signal when triggered
This commit is contained in:
parent
357b7eed94
commit
c1894dac73
|
|
@ -761,6 +761,7 @@ class LogicAnalyzerCore:
|
||||||
signals.append(signal)
|
signals.append(signal)
|
||||||
|
|
||||||
clock = writer.register_var("manta", "clk", "wire", size=1)
|
clock = writer.register_var("manta", "clk", "wire", size=1)
|
||||||
|
trigger = writer.register_var("manta", "trigger", "wire", size=1)
|
||||||
|
|
||||||
# add the data to each probe in the vcd file
|
# add the data to each probe in the vcd file
|
||||||
for timestamp in range(0, 2*len(capture_data)):
|
for timestamp in range(0, 2*len(capture_data)):
|
||||||
|
|
@ -768,6 +769,10 @@ class LogicAnalyzerCore:
|
||||||
# run the clock
|
# run the clock
|
||||||
writer.change(clock, timestamp, timestamp % 2 == 0)
|
writer.change(clock, timestamp, timestamp % 2 == 0)
|
||||||
|
|
||||||
|
# set the trigger
|
||||||
|
triggered = (timestamp // 2) >= self.trigger_loc
|
||||||
|
writer.change(trigger, timestamp, triggered)
|
||||||
|
|
||||||
# add other signals
|
# add other signals
|
||||||
for signal in signals:
|
for signal in signals:
|
||||||
var = signal["var"]
|
var = signal["var"]
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue