diff --git a/src/manta/__init__.py b/src/manta/__init__.py
index 1cd7421..34c3b33 100644
--- a/src/manta/__init__.py
+++ b/src/manta/__init__.py
@@ -761,6 +761,7 @@ class LogicAnalyzerCore:
                 signals.append(signal)
 
             clock = writer.register_var("manta", "clk", "wire", size=1)
+            trigger = writer.register_var("manta", "trigger", "wire", size=1)
 
             # add the data to each probe in the vcd file
             for timestamp in range(0, 2*len(capture_data)):
@@ -768,6 +769,10 @@ class LogicAnalyzerCore:
                 # run the clock
                 writer.change(clock, timestamp, timestamp % 2 == 0)
 
+                # set the trigger
+                triggered = (timestamp // 2) >= self.trigger_loc
+                writer.change(trigger, timestamp, triggered)
+
                 # add other signals
                 for signal in signals:
                     var = signal["var"]