From c1894dac73597be5d969d8808d6389e530fa925c Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Tue, 18 Apr 2023 01:22:01 -0400 Subject: [PATCH] add signal to vcd export to signal when triggered --- src/manta/__init__.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/manta/__init__.py b/src/manta/__init__.py index 1cd7421..34c3b33 100644 --- a/src/manta/__init__.py +++ b/src/manta/__init__.py @@ -761,6 +761,7 @@ class LogicAnalyzerCore: signals.append(signal) clock = writer.register_var("manta", "clk", "wire", size=1) + trigger = writer.register_var("manta", "trigger", "wire", size=1) # add the data to each probe in the vcd file for timestamp in range(0, 2*len(capture_data)): @@ -768,6 +769,10 @@ class LogicAnalyzerCore: # run the clock writer.change(clock, timestamp, timestamp % 2 == 0) + # set the trigger + triggered = (timestamp // 2) >= self.trigger_loc + writer.change(trigger, timestamp, triggered) + # add other signals for signal in signals: var = signal["var"]