From 9ac318150262cde90f2d8320673888fff952a883 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 7 Nov 2024 09:50:55 -0700 Subject: [PATCH] examples: fix typos --- examples/amaranth/uart_io_core.py | 2 +- examples/amaranth/uart_logic_analyzer.py | 2 +- examples/amaranth/uart_memory_core.py | 2 +- .../nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/examples/amaranth/uart_io_core.py b/examples/amaranth/uart_io_core.py index ca26c84..53c3a7c 100644 --- a/examples/amaranth/uart_io_core.py +++ b/examples/amaranth/uart_io_core.py @@ -13,7 +13,7 @@ class UARTIOCoreExample(Elaboratable): # Create Manta instance self.manta = Manta() - # Configure it to communicate over Ethernet + # Configure it to communicate over UART self.manta.interface = UARTInterface( port=port, baudrate=2000000, diff --git a/examples/amaranth/uart_logic_analyzer.py b/examples/amaranth/uart_logic_analyzer.py index 86c6118..0d6b539 100644 --- a/examples/amaranth/uart_logic_analyzer.py +++ b/examples/amaranth/uart_logic_analyzer.py @@ -13,7 +13,7 @@ class UARTLogicAnalyzerExample(Elaboratable): # Create Manta instance self.manta = Manta() - # Configure it to communicate over Ethernet + # Configure it to communicate over UART self.manta.interface = UARTInterface( port=port, baudrate=2000000, diff --git a/examples/amaranth/uart_memory_core.py b/examples/amaranth/uart_memory_core.py index f67fb1a..e0f2c83 100644 --- a/examples/amaranth/uart_memory_core.py +++ b/examples/amaranth/uart_memory_core.py @@ -11,7 +11,7 @@ class UARTMemoryCoreExample(Elaboratable): # Create Manta instance self.manta = Manta() - # Configure it to communicate over Ethernet + # Configure it to communicate over UART self.manta.interface = UARTInterface( port=port, baudrate=2000000, diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml index 8b413a2..7b29ec2 100644 --- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml +++ b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml @@ -31,6 +31,6 @@ ethernet: refclk_freq: 50e6 clk_freq: 50e6 - fpga_ip_addr: "192.168.0.110" - host_ip_addr: "192.168.0.100" + fpga_ip_addr: "10.0.0.2" + host_ip_addr: "10.0.0.1" udp_port: 2000