diff --git a/examples/verilog/icestick/io_core_uart/.gitignore b/examples/verilog/icestick/uart_io_core/.gitignore
similarity index 100%
rename from examples/verilog/icestick/io_core_uart/.gitignore
rename to examples/verilog/icestick/uart_io_core/.gitignore
diff --git a/examples/verilog/icestick/io_core_uart/blinky.py b/examples/verilog/icestick/uart_io_core/blinky.py
similarity index 100%
rename from examples/verilog/icestick/io_core_uart/blinky.py
rename to examples/verilog/icestick/uart_io_core/blinky.py
diff --git a/examples/verilog/icestick/io_core_uart/build.sh b/examples/verilog/icestick/uart_io_core/build.sh
similarity index 100%
rename from examples/verilog/icestick/io_core_uart/build.sh
rename to examples/verilog/icestick/uart_io_core/build.sh
diff --git a/examples/verilog/icestick/io_core_uart/manta.yaml b/examples/verilog/icestick/uart_io_core/manta.yaml
similarity index 100%
rename from examples/verilog/icestick/io_core_uart/manta.yaml
rename to examples/verilog/icestick/uart_io_core/manta.yaml
diff --git a/examples/verilog/icestick/io_core_uart/top_level.pcf b/examples/verilog/icestick/uart_io_core/top_level.pcf
similarity index 100%
rename from examples/verilog/icestick/io_core_uart/top_level.pcf
rename to examples/verilog/icestick/uart_io_core/top_level.pcf
diff --git a/examples/verilog/icestick/io_core_uart/top_level.sv b/examples/verilog/icestick/uart_io_core/top_level.sv
similarity index 100%
rename from examples/verilog/icestick/io_core_uart/top_level.sv
rename to examples/verilog/icestick/uart_io_core/top_level.sv
diff --git a/examples/verilog/icestick/logic_analyzer_uart/.gitignore b/examples/verilog/icestick/uart_logic_analyzer/.gitignore
similarity index 100%
rename from examples/verilog/icestick/logic_analyzer_uart/.gitignore
rename to examples/verilog/icestick/uart_logic_analyzer/.gitignore
diff --git a/examples/verilog/icestick/logic_analyzer_uart/build.sh b/examples/verilog/icestick/uart_logic_analyzer/build.sh
similarity index 100%
rename from examples/verilog/icestick/logic_analyzer_uart/build.sh
rename to examples/verilog/icestick/uart_logic_analyzer/build.sh
diff --git a/examples/verilog/icestick/logic_analyzer_uart/manta.yaml b/examples/verilog/icestick/uart_logic_analyzer/manta.yaml
similarity index 100%
rename from examples/verilog/icestick/logic_analyzer_uart/manta.yaml
rename to examples/verilog/icestick/uart_logic_analyzer/manta.yaml
diff --git a/examples/verilog/icestick/logic_analyzer_uart/top_level.pcf b/examples/verilog/icestick/uart_logic_analyzer/top_level.pcf
similarity index 100%
rename from examples/verilog/icestick/logic_analyzer_uart/top_level.pcf
rename to examples/verilog/icestick/uart_logic_analyzer/top_level.pcf
diff --git a/examples/verilog/icestick/logic_analyzer_uart/top_level.sv b/examples/verilog/icestick/uart_logic_analyzer/top_level.sv
similarity index 100%
rename from examples/verilog/icestick/logic_analyzer_uart/top_level.sv
rename to examples/verilog/icestick/uart_logic_analyzer/top_level.sv
diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore b/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/.gitignore
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore
rename to examples/verilog/nexys_a7/ether_logic_analyzer_io_core/.gitignore
diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.sh b/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/build.sh
similarity index 100%
rename from examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.sh
rename to examples/verilog/nexys_a7/ether_logic_analyzer_io_core/build.sh
diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.tcl b/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/build.tcl
similarity index 100%
rename from examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.tcl
rename to examples/verilog/nexys_a7/ether_logic_analyzer_io_core/build.tcl
diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv b/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/divider.sv
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv
rename to examples/verilog/nexys_a7/ether_logic_analyzer_io_core/divider.sv
diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/manta.yaml b/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/manta.yaml
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/manta.yaml
rename to examples/verilog/nexys_a7/ether_logic_analyzer_io_core/manta.yaml
diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/test.py b/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/test.py
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/test.py
rename to examples/verilog/nexys_a7/ether_logic_analyzer_io_core/test.py
diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv b/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/top_level.sv
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv
rename to examples/verilog/nexys_a7/ether_logic_analyzer_io_core/top_level.sv
diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.xdc b/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/top_level.xdc
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.xdc
rename to examples/verilog/nexys_a7/ether_logic_analyzer_io_core/top_level.xdc
diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/.gitignore b/examples/verilog/nexys_a7/uart_host_to_fpga_mem/.gitignore
similarity index 100%
rename from examples/verilog/nexys_a7/host_to_fpga_mem_uart/.gitignore
rename to examples/verilog/nexys_a7/uart_host_to_fpga_mem/.gitignore
diff --git a/examples/verilog/nexys_a7/io_core_uart/build.sh b/examples/verilog/nexys_a7/uart_host_to_fpga_mem/build.sh
similarity index 100%
rename from examples/verilog/nexys_a7/io_core_uart/build.sh
rename to examples/verilog/nexys_a7/uart_host_to_fpga_mem/build.sh
diff --git a/examples/verilog/nexys_a7/io_core_uart/build.tcl b/examples/verilog/nexys_a7/uart_host_to_fpga_mem/build.tcl
similarity index 100%
rename from examples/verilog/nexys_a7/io_core_uart/build.tcl
rename to examples/verilog/nexys_a7/uart_host_to_fpga_mem/build.tcl
diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/manta.yaml b/examples/verilog/nexys_a7/uart_host_to_fpga_mem/manta.yaml
similarity index 100%
rename from examples/verilog/nexys_a7/host_to_fpga_mem_uart/manta.yaml
rename to examples/verilog/nexys_a7/uart_host_to_fpga_mem/manta.yaml
diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.sv b/examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.sv
similarity index 100%
rename from examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.sv
rename to examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.sv
diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.xdc b/examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.xdc
similarity index 100%
rename from examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.xdc
rename to examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.xdc
diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/write.py b/examples/verilog/nexys_a7/uart_host_to_fpga_mem/write.py
similarity index 100%
rename from examples/verilog/nexys_a7/host_to_fpga_mem_uart/write.py
rename to examples/verilog/nexys_a7/uart_host_to_fpga_mem/write.py
diff --git a/examples/verilog/nexys_a7/io_core_uart/.gitignore b/examples/verilog/nexys_a7/uart_io_core/.gitignore
similarity index 100%
rename from examples/verilog/nexys_a7/io_core_uart/.gitignore
rename to examples/verilog/nexys_a7/uart_io_core/.gitignore
diff --git a/examples/verilog/nexys_a7/io_core_uart/blinky.py b/examples/verilog/nexys_a7/uart_io_core/blinky.py
similarity index 100%
rename from examples/verilog/nexys_a7/io_core_uart/blinky.py
rename to examples/verilog/nexys_a7/uart_io_core/blinky.py
diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.sh b/examples/verilog/nexys_a7/uart_io_core/build.sh
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.sh
rename to examples/verilog/nexys_a7/uart_io_core/build.sh
diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.tcl b/examples/verilog/nexys_a7/uart_io_core/build.tcl
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.tcl
rename to examples/verilog/nexys_a7/uart_io_core/build.tcl
diff --git a/examples/verilog/nexys_a7/io_core_uart/manta.yaml b/examples/verilog/nexys_a7/uart_io_core/manta.yaml
similarity index 100%
rename from examples/verilog/nexys_a7/io_core_uart/manta.yaml
rename to examples/verilog/nexys_a7/uart_io_core/manta.yaml
diff --git a/examples/verilog/nexys_a7/io_core_uart/top_level.sv b/examples/verilog/nexys_a7/uart_io_core/top_level.sv
similarity index 100%
rename from examples/verilog/nexys_a7/io_core_uart/top_level.sv
rename to examples/verilog/nexys_a7/uart_io_core/top_level.sv
diff --git a/examples/verilog/nexys_a7/io_core_uart/top_level.xdc b/examples/verilog/nexys_a7/uart_io_core/top_level.xdc
similarity index 100%
rename from examples/verilog/nexys_a7/io_core_uart/top_level.xdc
rename to examples/verilog/nexys_a7/uart_io_core/top_level.xdc
diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/.gitignore b/examples/verilog/nexys_a7/uart_logic_analyzer/.gitignore
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_uart/.gitignore
rename to examples/verilog/nexys_a7/uart_logic_analyzer/.gitignore
diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/build.sh b/examples/verilog/nexys_a7/uart_logic_analyzer/build.sh
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_uart/build.sh
rename to examples/verilog/nexys_a7/uart_logic_analyzer/build.sh
diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/build.tcl b/examples/verilog/nexys_a7/uart_logic_analyzer/build.tcl
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_uart/build.tcl
rename to examples/verilog/nexys_a7/uart_logic_analyzer/build.tcl
diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/manta.yaml b/examples/verilog/nexys_a7/uart_logic_analyzer/manta.yaml
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_uart/manta.yaml
rename to examples/verilog/nexys_a7/uart_logic_analyzer/manta.yaml
diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/top_level.sv b/examples/verilog/nexys_a7/uart_logic_analyzer/top_level.sv
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_uart/top_level.sv
rename to examples/verilog/nexys_a7/uart_logic_analyzer/top_level.sv
diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/top_level.xdc b/examples/verilog/nexys_a7/uart_logic_analyzer/top_level.xdc
similarity index 100%
rename from examples/verilog/nexys_a7/logic_analyzer_uart/top_level.xdc
rename to examples/verilog/nexys_a7/uart_logic_analyzer/top_level.xdc