From 6aea5cc6e1144e65b956d9368d062048928233c4 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 2 Mar 2024 12:52:04 -0800 Subject: [PATCH] update MemoryCore references --- doc/assets/memory_architecture.drawio.svg | 66 +++++++++++------------ src/manta/logic_analyzer/__init__.py | 7 +-- src/manta/manta.py | 7 ++- test/test_mem_core_hw.py | 4 +- 4 files changed, 41 insertions(+), 43 deletions(-) diff --git a/doc/assets/memory_architecture.drawio.svg b/doc/assets/memory_architecture.drawio.svg index ef58678..c929ee4 100644 --- a/doc/assets/memory_architecture.drawio.svg +++ b/doc/assets/memory_architecture.drawio.svg @@ -1,4 +1,4 @@ - + - + @@ -103,7 +101,7 @@ -
+
addr @@ -121,7 +119,7 @@ -
+
din @@ -129,7 +127,7 @@
- + din @@ -139,7 +137,7 @@ -
+
dout @@ -157,7 +155,7 @@ -
+
we @@ -258,12 +256,12 @@ - + -
+
user_addr @@ -276,8 +274,8 @@ - - + + @@ -289,17 +287,17 @@
- + user_din - - + + -
+
user_dout @@ -312,21 +310,21 @@ - - + + -
+
- user_we + user_write_enable
- user_we + user_write_enable @@ -353,7 +351,7 @@ -
+
din @@ -361,7 +359,7 @@
- + din @@ -476,7 +474,7 @@ -
+
din @@ -484,7 +482,7 @@
- + din @@ -603,12 +601,12 @@ - - + + -
+
bus @@ -616,17 +614,17 @@
- + bus - - + + -
+
bus @@ -634,7 +632,7 @@
- + bus diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index c3f7c26..3f091f6 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -36,7 +36,8 @@ class LogicAnalyzerCore(Elaboratable): self._probes, self._fsm.get_max_addr() + 1, interface ) - self._sample_mem = ReadOnlyMemoryCore( + self._sample_mem = MemoryCore( + mode = "fpga_to_host", width=sum(self._config["probes"].values()), depth=self._config["sample_depth"], base_addr=self._trig_blk.get_max_addr() + 1, @@ -158,7 +159,7 @@ class LogicAnalyzerCore(Elaboratable): # Concat all the probes together, and feed to input of sample memory # (it is necessary to reverse the order such that first probe occupies # the lowest location in memory) - m.d.comb += self._sample_mem.user_data.eq(Cat(self._probes[::-1])) + m.d.comb += self._sample_mem.user_data_in.eq(Cat(self._probes[::-1])) # Wire bus connections between internal modules m.d.comb += [ @@ -170,7 +171,7 @@ class LogicAnalyzerCore(Elaboratable): # Non-bus Connections self._fsm.trigger.eq(self._trig_blk.trig), self._sample_mem.user_addr.eq(self._fsm.write_pointer), - self._sample_mem.user_we.eq(self._fsm.write_enable), + self._sample_mem.user_write_enable.eq(self._fsm.write_enable), ] return m diff --git a/src/manta/manta.py b/src/manta/manta.py index 424a40a..cf2bd09 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -80,9 +80,8 @@ class Manta(Elaboratable): def _get_cores(self): """ - Creates instances of the cores (IOCore, LogicAnalyzerCore, - ReadOnlyMemoryCore) specified in the user's configuration, and returns - them as a list. + Creates instances of the cores (IOCore, LogicAnalyzerCore, MemoryCore) + specified in the user's configuration, and returns them as a list. """ self._cores = {} @@ -95,7 +94,7 @@ class Manta(Elaboratable): core = LogicAnalyzerCore(attrs, base_addr, self.interface) elif attrs["type"] == "memory_read_only": - core = ReadOnlyMemoryCore.from_config(attrs, base_addr, self.interface) + core = MemoryCore.from_config(attrs, base_addr, self.interface) # Make sure we're not out of address space if core.get_max_addr() > (2**16) - 1: diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 78bd024..3a5d7b5 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -73,8 +73,8 @@ class MemoryCoreLoopbackTest(Elaboratable): m.d.comb += [ self.manta.mem_core.user_addr.eq(addr), - self.manta.mem_core.user_data.eq(data), - self.manta.mem_core.user_we.eq(we), + self.manta.mem_core.user_data_in.eq(data), + self.manta.mem_core.user_write_enable.eq(we), self.manta.interface.rx.eq(uart_pins.rx.i), uart_pins.tx.o.eq(self.manta.interface.tx), ]