From 4abc2e2caed69591cc30b6de47853f1e4f22207d Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 31 Jul 2023 06:54:32 -0700 Subject: [PATCH] update template naming for consistency --- src/manta/uart_iface/__init__.py | 4 ++-- ...e_rx_inst_templ.v => uart_rx_bridge_rx_inst_tmpl.v} | 0 ...e_tx_inst_templ.v => uart_tx_bridge_tx_inst_tmpl.v} | 0 test/auto_gen/valid_configs/2_lut_ram.yaml | 10 ---------- 4 files changed, 2 insertions(+), 12 deletions(-) rename src/manta/uart_iface/{uart_rx_bridge_rx_inst_templ.v => uart_rx_bridge_rx_inst_tmpl.v} (100%) rename src/manta/uart_iface/{uart_tx_bridge_tx_inst_templ.v => uart_tx_bridge_tx_inst_tmpl.v} (100%) delete mode 100644 test/auto_gen/valid_configs/2_lut_ram.yaml diff --git a/src/manta/uart_iface/__init__.py b/src/manta/uart_iface/__init__.py index b4081c6..152dc39 100644 --- a/src/manta/uart_iface/__init__.py +++ b/src/manta/uart_iface/__init__.py @@ -176,11 +176,11 @@ class UARTInterface: return bridge_tx_def + '\n' + uart_tx_def def rx_hdl_inst(self): - rx = VerilogManipulator("uart_iface/uart_rx_bridge_rx_inst_templ.v") + rx = VerilogManipulator("uart_iface/uart_rx_bridge_rx_inst_tmpl.v") rx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */") return rx.get_hdl() def tx_hdl_inst(self): - tx = VerilogManipulator("uart_iface/uart_tx_bridge_tx_inst_templ.v") + tx = VerilogManipulator("uart_iface/uart_tx_bridge_tx_inst_tmpl.v") tx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */") return tx.get_hdl() \ No newline at end of file diff --git a/src/manta/uart_iface/uart_rx_bridge_rx_inst_templ.v b/src/manta/uart_iface/uart_rx_bridge_rx_inst_tmpl.v similarity index 100% rename from src/manta/uart_iface/uart_rx_bridge_rx_inst_templ.v rename to src/manta/uart_iface/uart_rx_bridge_rx_inst_tmpl.v diff --git a/src/manta/uart_iface/uart_tx_bridge_tx_inst_templ.v b/src/manta/uart_iface/uart_tx_bridge_tx_inst_tmpl.v similarity index 100% rename from src/manta/uart_iface/uart_tx_bridge_tx_inst_templ.v rename to src/manta/uart_iface/uart_tx_bridge_tx_inst_tmpl.v diff --git a/test/auto_gen/valid_configs/2_lut_ram.yaml b/test/auto_gen/valid_configs/2_lut_ram.yaml deleted file mode 100644 index 10d43ef..0000000 --- a/test/auto_gen/valid_configs/2_lut_ram.yaml +++ /dev/null @@ -1,10 +0,0 @@ ---- -cores: - my_lut_mem: - type: lut_mem - size: 64 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file