diff --git a/src/manta/uart_iface/__init__.py b/src/manta/uart_iface/__init__.py
index b4081c6..152dc39 100644
--- a/src/manta/uart_iface/__init__.py
+++ b/src/manta/uart_iface/__init__.py
@@ -176,11 +176,11 @@ class UARTInterface:
         return bridge_tx_def + '\n' + uart_tx_def
 
     def rx_hdl_inst(self):
-        rx = VerilogManipulator("uart_iface/uart_rx_bridge_rx_inst_templ.v")
+        rx = VerilogManipulator("uart_iface/uart_rx_bridge_rx_inst_tmpl.v")
         rx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */")
         return rx.get_hdl()
 
     def tx_hdl_inst(self):
-        tx = VerilogManipulator("uart_iface/uart_tx_bridge_tx_inst_templ.v")
+        tx = VerilogManipulator("uart_iface/uart_tx_bridge_tx_inst_tmpl.v")
         tx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */")
         return tx.get_hdl()
\ No newline at end of file
diff --git a/src/manta/uart_iface/uart_rx_bridge_rx_inst_templ.v b/src/manta/uart_iface/uart_rx_bridge_rx_inst_tmpl.v
similarity index 100%
rename from src/manta/uart_iface/uart_rx_bridge_rx_inst_templ.v
rename to src/manta/uart_iface/uart_rx_bridge_rx_inst_tmpl.v
diff --git a/src/manta/uart_iface/uart_tx_bridge_tx_inst_templ.v b/src/manta/uart_iface/uart_tx_bridge_tx_inst_tmpl.v
similarity index 100%
rename from src/manta/uart_iface/uart_tx_bridge_tx_inst_templ.v
rename to src/manta/uart_iface/uart_tx_bridge_tx_inst_tmpl.v
diff --git a/test/auto_gen/valid_configs/2_lut_ram.yaml b/test/auto_gen/valid_configs/2_lut_ram.yaml
deleted file mode 100644
index 10d43ef..0000000
--- a/test/auto_gen/valid_configs/2_lut_ram.yaml
+++ /dev/null
@@ -1,10 +0,0 @@
----
-cores:
-  my_lut_mem:
-    type: lut_mem
-    size: 64
-
-uart:
-  port: "auto"
-  baudrate: 115200
-  clock_freq: 100000000
\ No newline at end of file