From 13bc196a34588f280153a770fc2fc7eaeb6e6df4 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 12 May 2024 10:35:18 -0700 Subject: [PATCH] rename Nexys A7 to Nexys 4 DDR --- doc/repository_structure.md | 4 ++-- .../ether_logic_analyzer_io_core/.gitignore | 0 .../ether_logic_analyzer_io_core/build.sh | 0 .../ether_logic_analyzer_io_core/build.tcl | 0 .../ether_logic_analyzer_io_core/divider.sv | 0 .../ether_logic_analyzer_io_core/manta.yaml | 0 .../ether_logic_analyzer_io_core/test.py | 0 .../ether_logic_analyzer_io_core/top_level.sv | 0 .../ether_logic_analyzer_io_core/top_level.xdc | 0 .../{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/.gitignore | 0 .../{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/build.sh | 0 .../{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/build.tcl | 0 .../{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/manta.yaml | 0 .../uart_host_to_fpga_mem/top_level.sv | 0 .../uart_host_to_fpga_mem/top_level.xdc | 2 +- .../{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/write.py | 0 .../verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/.gitignore | 0 .../verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/blinky.py | 0 .../verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/build.sh | 0 .../verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/build.tcl | 0 .../verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/manta.yaml | 0 .../{nexys_a7 => nexys4_ddr}/uart_io_core/top_level.sv | 0 .../{nexys_a7 => nexys4_ddr}/uart_io_core/top_level.xdc | 2 +- .../{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/.gitignore | 0 .../{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/build.sh | 0 .../{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/build.tcl | 0 .../{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/manta.yaml | 0 .../{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/top_level.sv | 0 .../uart_logic_analyzer/top_level.xdc | 2 +- test/test_toolchains.py | 2 +- 30 files changed, 6 insertions(+), 6 deletions(-) rename examples/verilog/{nexys_a7 => nexys4_ddr}/ether_logic_analyzer_io_core/.gitignore (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/ether_logic_analyzer_io_core/build.sh (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/ether_logic_analyzer_io_core/build.tcl (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/ether_logic_analyzer_io_core/divider.sv (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/ether_logic_analyzer_io_core/manta.yaml (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/ether_logic_analyzer_io_core/test.py (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/ether_logic_analyzer_io_core/top_level.sv (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/ether_logic_analyzer_io_core/top_level.xdc (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/.gitignore (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/build.sh (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/build.tcl (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/manta.yaml (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/top_level.sv (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/top_level.xdc (99%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_host_to_fpga_mem/write.py (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/.gitignore (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/blinky.py (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/build.sh (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/build.tcl (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/manta.yaml (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/top_level.sv (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_io_core/top_level.xdc (99%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/.gitignore (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/build.sh (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/build.tcl (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/manta.yaml (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/top_level.sv (100%) rename examples/verilog/{nexys_a7 => nexys4_ddr}/uart_logic_analyzer/top_level.xdc (99%) diff --git a/doc/repository_structure.md b/doc/repository_structure.md index 6fc6d3f..252f5ba 100644 --- a/doc/repository_structure.md +++ b/doc/repository_structure.md @@ -2,7 +2,7 @@ - `src/manta/` contains the Python source needed to generate and run the cores. - `test/` contains Manta's tests, which are a mix of functional simulations and hardware-in-the-loop testing. These tests leverage the `pytest` testing framework. - `doc/` contains the documentation you're reading right now! -- `examples/` contains examples for both the Digilent Nexys 4 DDR/Nexys A7 with thier onboard Series-7, as well as the Icestick with its onboard iCE40. +- `examples/` contains examples of Manta being used in designs for a handful of FPGA boards. - `.github/` contains GitHub Actions workflows for automatically running the tests and building the documentation site on every commit. ## Tools Used @@ -12,4 +12,4 @@ - [GitHub Actions](https://docs.github.com/en/actions) is used for continuous integration. ## GitHub Actions Setup -Since Vivado is large and requires individual licenses, it is run on a private server, which is configured as a self-hosted runner in GitHub Actions. This is a virtual server hosted with KVM/QEMU and managed by libvirt, which is configured as transient so that it reloads its state from a snapshot periodically. A Nexys A7 and Icestick are connected to the physical machine and passthrough-ed to this VM so that continuous integration can check against real hardware. \ No newline at end of file +Since Vivado is large and requires individual licenses, it is run on a private server, which is configured as a self-hosted runner in GitHub Actions. This is a virtual server hosted with KVM/QEMU and managed by libvirt, which is configured as transient so that it reloads its state from a snapshot periodically. A Nexys4 DDR and Icestick are connected to the physical machine and passthrough-ed to this VM so that continuous integration can check against real hardware. \ No newline at end of file diff --git a/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/.gitignore b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/.gitignore similarity index 100% rename from examples/verilog/nexys_a7/ether_logic_analyzer_io_core/.gitignore rename to examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/.gitignore diff --git a/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/build.sh b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh similarity index 100% rename from examples/verilog/nexys_a7/ether_logic_analyzer_io_core/build.sh rename to examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh diff --git a/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/build.tcl b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl similarity index 100% rename from examples/verilog/nexys_a7/ether_logic_analyzer_io_core/build.tcl rename to examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl diff --git a/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/divider.sv b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/divider.sv similarity index 100% rename from examples/verilog/nexys_a7/ether_logic_analyzer_io_core/divider.sv rename to examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/divider.sv diff --git a/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/manta.yaml b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml similarity index 100% rename from examples/verilog/nexys_a7/ether_logic_analyzer_io_core/manta.yaml rename to examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml diff --git a/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/test.py b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/test.py similarity index 100% rename from examples/verilog/nexys_a7/ether_logic_analyzer_io_core/test.py rename to examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/test.py diff --git a/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/top_level.sv b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.sv similarity index 100% rename from examples/verilog/nexys_a7/ether_logic_analyzer_io_core/top_level.sv rename to examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.sv diff --git a/examples/verilog/nexys_a7/ether_logic_analyzer_io_core/top_level.xdc b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.xdc similarity index 100% rename from examples/verilog/nexys_a7/ether_logic_analyzer_io_core/top_level.xdc rename to examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.xdc diff --git a/examples/verilog/nexys_a7/uart_host_to_fpga_mem/.gitignore b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/.gitignore similarity index 100% rename from examples/verilog/nexys_a7/uart_host_to_fpga_mem/.gitignore rename to examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/.gitignore diff --git a/examples/verilog/nexys_a7/uart_host_to_fpga_mem/build.sh b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh similarity index 100% rename from examples/verilog/nexys_a7/uart_host_to_fpga_mem/build.sh rename to examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh diff --git a/examples/verilog/nexys_a7/uart_host_to_fpga_mem/build.tcl b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl similarity index 100% rename from examples/verilog/nexys_a7/uart_host_to_fpga_mem/build.tcl rename to examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl diff --git a/examples/verilog/nexys_a7/uart_host_to_fpga_mem/manta.yaml b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/manta.yaml similarity index 100% rename from examples/verilog/nexys_a7/uart_host_to_fpga_mem/manta.yaml rename to examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/manta.yaml diff --git a/examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.sv b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.sv similarity index 100% rename from examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.sv rename to examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.sv diff --git a/examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.xdc b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.xdc similarity index 99% rename from examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.xdc rename to examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.xdc index 6184324..2dbee5f 100644 --- a/examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.xdc +++ b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.xdc @@ -3,7 +3,7 @@ ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 +## This file has been modified from the default .xdc provided by Digilent for the Nexys 4 DDR ## Clock signal - uncomment _both_ of these lines to create clk_100mhz set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk diff --git a/examples/verilog/nexys_a7/uart_host_to_fpga_mem/write.py b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/write.py similarity index 100% rename from examples/verilog/nexys_a7/uart_host_to_fpga_mem/write.py rename to examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/write.py diff --git a/examples/verilog/nexys_a7/uart_io_core/.gitignore b/examples/verilog/nexys4_ddr/uart_io_core/.gitignore similarity index 100% rename from examples/verilog/nexys_a7/uart_io_core/.gitignore rename to examples/verilog/nexys4_ddr/uart_io_core/.gitignore diff --git a/examples/verilog/nexys_a7/uart_io_core/blinky.py b/examples/verilog/nexys4_ddr/uart_io_core/blinky.py similarity index 100% rename from examples/verilog/nexys_a7/uart_io_core/blinky.py rename to examples/verilog/nexys4_ddr/uart_io_core/blinky.py diff --git a/examples/verilog/nexys_a7/uart_io_core/build.sh b/examples/verilog/nexys4_ddr/uart_io_core/build.sh similarity index 100% rename from examples/verilog/nexys_a7/uart_io_core/build.sh rename to examples/verilog/nexys4_ddr/uart_io_core/build.sh diff --git a/examples/verilog/nexys_a7/uart_io_core/build.tcl b/examples/verilog/nexys4_ddr/uart_io_core/build.tcl similarity index 100% rename from examples/verilog/nexys_a7/uart_io_core/build.tcl rename to examples/verilog/nexys4_ddr/uart_io_core/build.tcl diff --git a/examples/verilog/nexys_a7/uart_io_core/manta.yaml b/examples/verilog/nexys4_ddr/uart_io_core/manta.yaml similarity index 100% rename from examples/verilog/nexys_a7/uart_io_core/manta.yaml rename to examples/verilog/nexys4_ddr/uart_io_core/manta.yaml diff --git a/examples/verilog/nexys_a7/uart_io_core/top_level.sv b/examples/verilog/nexys4_ddr/uart_io_core/top_level.sv similarity index 100% rename from examples/verilog/nexys_a7/uart_io_core/top_level.sv rename to examples/verilog/nexys4_ddr/uart_io_core/top_level.sv diff --git a/examples/verilog/nexys_a7/uart_io_core/top_level.xdc b/examples/verilog/nexys4_ddr/uart_io_core/top_level.xdc similarity index 99% rename from examples/verilog/nexys_a7/uart_io_core/top_level.xdc rename to examples/verilog/nexys4_ddr/uart_io_core/top_level.xdc index 82c04c3..695ff17 100644 --- a/examples/verilog/nexys_a7/uart_io_core/top_level.xdc +++ b/examples/verilog/nexys4_ddr/uart_io_core/top_level.xdc @@ -3,7 +3,7 @@ ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 +## This file has been modified from the default .xdc provided by Digilent for the Nexys 4 DDR ## Clock signal - uncomment _both_ of these lines to create clk_100mhz set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk diff --git a/examples/verilog/nexys_a7/uart_logic_analyzer/.gitignore b/examples/verilog/nexys4_ddr/uart_logic_analyzer/.gitignore similarity index 100% rename from examples/verilog/nexys_a7/uart_logic_analyzer/.gitignore rename to examples/verilog/nexys4_ddr/uart_logic_analyzer/.gitignore diff --git a/examples/verilog/nexys_a7/uart_logic_analyzer/build.sh b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh similarity index 100% rename from examples/verilog/nexys_a7/uart_logic_analyzer/build.sh rename to examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh diff --git a/examples/verilog/nexys_a7/uart_logic_analyzer/build.tcl b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl similarity index 100% rename from examples/verilog/nexys_a7/uart_logic_analyzer/build.tcl rename to examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl diff --git a/examples/verilog/nexys_a7/uart_logic_analyzer/manta.yaml b/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml similarity index 100% rename from examples/verilog/nexys_a7/uart_logic_analyzer/manta.yaml rename to examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml diff --git a/examples/verilog/nexys_a7/uart_logic_analyzer/top_level.sv b/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.sv similarity index 100% rename from examples/verilog/nexys_a7/uart_logic_analyzer/top_level.sv rename to examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.sv diff --git a/examples/verilog/nexys_a7/uart_logic_analyzer/top_level.xdc b/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.xdc similarity index 99% rename from examples/verilog/nexys_a7/uart_logic_analyzer/top_level.xdc rename to examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.xdc index 81c1998..f234e47 100644 --- a/examples/verilog/nexys_a7/uart_logic_analyzer/top_level.xdc +++ b/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.xdc @@ -3,7 +3,7 @@ ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 +## This file has been modified from the default .xdc provided by Digilent for the Nexys4 DDR ## Clock signal - uncomment _both_ of these lines to create clk_100mhz set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk diff --git a/test/test_toolchains.py b/test/test_toolchains.py index c21c26a..1ddc98d 100644 --- a/test/test_toolchains.py +++ b/test/test_toolchains.py @@ -6,7 +6,7 @@ import pytest @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") -def test_arty_a7_tools(): +def test_nexys4_ddr_tools(): Nexys4DDRPlatform().build(Blinky(), do_program=False)