manta/test/test_verilog_gen.yaml

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---
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cores:
io_core:
type: io
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inputs:
probe0: 1
probe1: 2
probe2: 8
probe3: 20
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outputs:
probe4:
width: 1
initial_value: 1
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probe5:
width: 2
initial_value: 2
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probe6: 8
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probe7:
width: 20
initial_value: 65538
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uart:
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port: "/dev/ttyUSB1"
baudrate: 115200
clock_freq: 12000000