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test_bridge_rx_sim.py
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refactor uart into multiple files
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2024-01-07 21:54:14 -08:00 |
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test_bridge_tx_sim.py
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revert UART and InternalBus() refactor
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2024-01-07 21:39:44 -08:00 |
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test_io_core_hw.py
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update submodule usage, tidy logic analyzer config check
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2024-01-14 12:51:52 -08:00 |
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test_io_core_sim.py
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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test_logic_analyzer_fsm_sim.py
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refactor logic analyzer FSM to be sequential-only for better timing
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2024-01-21 23:45:14 -08:00 |
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test_logic_analyzer_hw.py
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update submodule usage, tidy logic analyzer config check
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2024-01-14 12:51:52 -08:00 |
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test_logic_analyzer_sim.py
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complete refactor to InternalBus()
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2024-01-07 22:35:15 -08:00 |
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test_mem_core_hw.py
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update submodule usage, tidy logic analyzer config check
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2024-01-14 12:51:52 -08:00 |
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test_mem_core_sim.py
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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test_source_bridge_sim.py
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add first pass at ethernet
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2024-01-28 21:54:46 -08:00 |
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test_toolchains.py
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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test_uart_rx_sim.py
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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test_uart_tx_sim.py
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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test_verilog_gen.py
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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test_verilog_gen.yaml
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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