for sticky labels making connections through the hierarchy. This
is only needed for some annoying layouts that put point-size labels
with no connecting geometry in cells, and causes magic to spent
excessive amounts of time searching through labels for any layout
that has lots of labels.
not restored until after all cells have been processed through
extraction. Otherwise, top-down connections can end up with
different generated names for the same node, resulting in a
disconnect in the netlist.
extracting substrate regions, due to failure to clean up the tagged
tiles after exiting a search due to finding a substrate type that
was not the global substrate.
subcells that do not have deep nwell. This commit handles the
case where the pwell region is explicitly marked with a layer
type. To do: Handle the case where the pwell region is implicit.
statement in a .ext file require that all aliases of a node name be
rehashed after a node merge, or else node loops can occur. Also
prevented statements of the form "equiv A A" from being output in
the .ext file, as they are useless.
The previous behavior was to generate hierarchical names for all
labels when copying contents of subcells. This is "safe" for
copying selections without accidentally shorting things through
labeling, but it can make a mess of the selection. Options are
now "select do labels" for the existing behavior, "select no labels"
to not show any labels, and "select simple labels" to show only the
root name of labels in subcells.
unique will also be assigned a unique port index at the end of the
port list. That ensures that the unique names are all properly
found in the extracted .subckt for the cell.
asymmetric MOSFET definitions in the tech file "extract" section.
Corrected the nmos.tech.in file to put the resistance classes in
plane order, as otherwise the interpretation of which resistance
classes belongs to the transistor source and drain can get messed
up by the presence of buried contacts.
to stop the search whenever a cell is not found. Used this to implement
a new option for GDS writes, "gds undefined allow|disallow" (default
"disallow") controls whether or not GDS with undefined references will
be allowed to be written. Similarly affects CIF and LEF writes, extraction,
and DRC (when running "drc check" from the top).
restricted to its original intent, which is to replace the long name
formed from the plane short name and the "minfinity" coordinate.
This avoids issues with conflicting substrate names derived from a
real layer such as pwell. Also, the global substrate node name now
returns the variable name without the "$" in front if the variable
has not been set to anything. This avoids potential syntax errors
in the netlist.
one terminal of a device as the substrate, but also specifies
shielding types for the substrate, then the extraction cannot just
assume that a missing terminal is connected to the substrate without
first checking that there are no substrate shielding types under the
device.
could have multiple ports of the same name. This problem had been
worked over before, but there was an indpendent mechanism producing
the same result for a completely different reason, caused by subcells
being much larger than the cookie-cutter extraction method's extraction
regions. Solved by tracking port names in a hash table and preventing
re-use. (2) ext2spice was producing "no such node" errors; like (1)
this had been previously worked on, and like (1) this mechanism was
independent. Problem came from not passing -1 to extHierSubstrate for
the non-arrayed dimension of a 1-dimensional array. Also: Removed
the word "fatal" from extraction error reporting, as nearly all
extraction errors are entirely benign. This should clear up confusion
among alarmed end-users.
unique" code. It was using DBEraseLabelsByContent() which would
erase all matching labels, and could potentially erase labels that
were still remaining on the list being processed, causing a segfault.
Also corrected minor errors identified by valgrind during debugging
the above-referenced problem.
such that it looks for material connecting to the label at the
center point of the label and not the lower left corner. This keeps
the behavior of looking for tiles on the corners of a degenerate
label line or point between layers, but avoids problems with sticky
labels that are not quite aligned with the rectangle (due to certain
commercial EDA tools that have a sloppier notion of labeling).
p device; this was previously dependent only on the first character
of the extracted device model name. Since the tech file has control
over what the device layer names are but not the extracted model
names, the device layer type name is used as a backup way to determine
if the type is n or p, if that cannot be determined from the extracted
model name.
with two or more terminals other than the device identifier type
tied together) would fail if there were not a device record
specifically matching a one-S/D-terminal device. This is
inconsistent with past behavior, and so has been fixed.
because the opposite type (pwell) is not directly underneath the
gate, but touches it on the plane below. Because the pwell may
be represented by space tiles on the well plane, it was also
necessary to deal with the space type in the bitmask.
type in the device record, which was not updated at the end of
checking terminals for matching device extraction types. so the
boundary survey might see the wrong device type and generate an
incorrect boundary survey as a result.
support asymmetric FETs and other devices like bipolars that have
three distinct terminals. This does not go as far as it should to
make the array independent of the number of declared terminals of
the device. However, it suffices to make, e.g., parameter "a2=area"
work for a bipolar device, and to generate the right drain and source
areas and perimeters for asymmetric (e.g., extended-drain) devices.
device layer type to describe the extraction for both a regular FET
and an extended-drain device. Note that the current code still
requires that the extended-drain device be declared first, and does
not check for this or attempt to reorder if incorrect.
supposed to pull "sticky labels" into the cumulative flattened
layout. Because it failed to check for the "sticky" flag, it
would copy all labels, causing extraction time to go exponential
as the number of labels in the design increases. Based on this
correction, the extHierConnectFunc1() routine should be able to
be optimized by stopping the search for sticky labels on the first
non-sticky label, since extSubtreeFunc() ensures that all sticky
labels come first in the label list.
the extractor was not checking temp_subsname as well as glob_subsname,
and so was failing to apply the substrate name to child cells in
"merge" statements in the extract file, causing the substrate to get
disconnected between parent and child.
works for the first pair of types/plane being below the second pair of
types/plane (upward fringing from the top of a wire to an overlapping
wire above it), which was not being handled due to an implicit assumption
that plane1 < plane2, which does not have to be the case.
could cause serious errors on systems that do not auto-zero allocated
memory. Also: Fixed an error introduced by a recent commit to allocate
character memory for efReadLine() which frees the memory before reading
a .res.ext file, causing a crash when using "ext2spice" with the
"extresist on" option.
optional name field to the "substrate" line in the extract section
of the techfile. This is the default name of the substrate if not
connected to anything labeled. It may use a Tcl variable (preferred).
(2) Added command option "instance orientation [-def]" that returns
the orientation of the named or selected instance. The -def option
returns the orientation using DEF naming convention; otherwise, the
naming used with "getcell" is generated.
areas and writes ANTENNAGATEAREA and ANTENNADIFFAREA values.
(2) Determines "USE POWER" or "USE GROUND" from label names
matching Tcl variables $VDD and $GND, if the USE has not been
registered as a cell property (knowning the use allows magic
to avoid writing an ANTENNADIFFAREA for power rails, although
doing so should not be an issue).
not copy labels; not copying labels speeds up the antenna checks
(which don't need labels) greatly. Also fixed several numerical
overflow problems in the antenna checks, which resulted in false
positive errors, as well as nonsensical results.
Conflicts:
VERSION
Merged recent changes from master back into bplane, as the efficiency of
bplane for doing extraction on large layouts is unquestionably better.
Fixed the implementation of DBMoveCell() for bplane. Corrected an error
in the bplane version of dbScaleCell() that enumerates cell uses but
does not free the list.
Tim Edwards
Dan Moore