The '&' has higher precedence, so the expression of the '&' side receive
extra parentheses.
ResMakeRes.c:671:37: warning: suggest parentheses around '&&' within '||'
ResMakeRes.c:942:32: warning: suggest parentheses around '&&' within '||'
ResSimple.c:201:70: warning: suggest parentheses around '&&' within '||'
ResRex.c:1036:28: warning: suggest parentheses around '&&' within '||'
ResRex.c:1038:50: warning: suggest parentheses around '&&' within '||'
ext2sim.c:1341:47: warning: suggest parentheses around '&&' within '||'
ext2spice.c:172:44: warning: suggest parentheses around '&&' within '||'
ext2spice.c:173:49: warning: suggest parentheses around '&&' within '||'
ext2spice.c:3655:50: warning: suggest parentheses around '&&' within '||'
ext2hier.c:1412:50: warning: suggest parentheses around '&&' within '||'
gcrDebug.c:638:55: warning: suggest parentheses around '&&' within '||'
selEnum.c:323:28: warning: suggest parentheses around '&&' within '||'
GCC14 -Wall cleanup series [-Wparentheses]
PlowRules1.c:439:9: warning: suggest parentheses around assignment used as truth value
PlowTech.c:645:17: warning: suggest parentheses around assignment used as truth value
PlowTech.c:652:17: warning: suggest parentheses around assignment used as truth value
PlowTech.c:1019:17: warning: suggest parentheses around assignment used as truth value
ResReadSim.c:270:13: warning: suggest parentheses around assignment used as truth value
ResReadSim.c:871:9: warning: suggest parentheses around assignment used as truth value
ResRex.c:1840:17: warning: suggest parentheses around assignment used as truth value
getrect.c:72:9: warning: suggest parentheses around assignment used as truth value
getrect.c:79:9: warning: suggest parentheses around assignment used as truth value
getrect.c:86:9: warning: suggest parentheses around assignment used as truth value
getrect.c:93:9: warning: suggest parentheses around assignment used as truth value
hash.c:732:16: warning: suggest parentheses around assignment used as truth value
heap.c:328:17: warning: suggest parentheses around assignment used as truth value
heap.c:344:17: warning: suggest parentheses around assignment used as truth value
netlist.c:323:17: warning: suggest parentheses around assignment used as truth value
niceabort.c:121:9: warning: suggest parentheses around assignment used as truth value
path.c:1102:12: warning: suggest parentheses around assignment used as truth value
pathvisit.c:245:13: warning: suggest parentheses around assignment used as truth value
pathvisit.c:295:17: warning: suggest parentheses around assignment used as truth value
tech.c:656:17: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1591:16: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1622:16: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1813:12: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1862:12: warning: suggest parentheses around assignment used as truth value
ext2spice.c:3808:16: warning: suggest parentheses around assignment used as truth value
CalmaRdio.c:437:9: warning: suggest parentheses around assignment used as truth value
CalmaWrite.c:396:9: warning: suggest parentheses around assignment used as truth value
CalmaWrite.c:1772:29: warning: suggest parentheses around assignment used as truth value
CalmaWriteZ.c:372:9: warning: suggest parentheses around assignment used as truth value
CalmaWriteZ.c:1608:29: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:209:9: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:214:9: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:220:9: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:226:9: warning: suggest parentheses around assignment used as truth value
CIFrdutils.c:1258:12: warning: suggest parentheses around assignment used as truth value
GCC14 -Wall cleanup series [-Wparentheses]
a transistor's first tile record is a well or substrate type;
normally this is avoided, but if that's the only device terminal
that connects to the node, it will be used. Also changed the
code to not report a failure when space is found under the
device, when space is allowed as a substrate type. Instead it
will print a message that the substrate is not being extracted as
a resistive network. However, note that the correct solution is
to do what the regular "extract" code does, which is to paint the
substrate type in the cell area first, so that there are valid
tile types to use for extracting the substrate network.
missing from a netlist generated by ext2spice with the "extresist"
option enabled. The first had to do with some parts of nets being
given alias names for a net, and the second was caused during
"extresist" and would also result in error messages about devices
missing terminals.
routine that marks resistors in loops to prevent infinite
recursion, but later incorrectly eliminates those resistors.
Also: Changed the "tolerance" command to affect only the R-C
time constant tolerance. Added a "threshold" command option
that limits output of small resistors. This can help reduce
large networks that are otherwise not reducible by the three
methods of reduction (serial, parallel, and delta-wye), but
does affect output values (slightly). This will probably need
to be revisited at some point.
command for use with "extract path"; the cellname was being cleared
after generating the filename with the extract path, but was being
used afterward, so it needed to be reverted back to the original
value, not just free'd. Otherwise "extresist" will fail to produce
any results.
".res.ext" file from "extresist" after using "extract do local" (and
probably with "extract path" as well). Fixed this, and also made
sure that "extresist" writes the ".res.ext" file to the same location
as ".ext" always, so that handling is consistent throughout the
full R-C extraction process, across the use of "extract", "ext2sim",
"extresist", and "ext2spice".
causing the SI suffix not to be the expected one. Adjusted the
bounds where each SI suffix is used to keep output in the range of
0.1 to 100, although the boundary is very subjective. Made a
correction to the extresist code to scan through all device records
for a tile type. However, (1) there are cases being missed, and (2)
this should not be necessary since all device types should be able
to be known exactly from the contents of the .sim file. Needs more
work.
natural sort instead of ASCII-based sorting, so that ports that
are numbered arrays will be indexed properly by count. Also:
Modified the "extresist" handling of substrate to draw the default
substrate type over the entire cell area (less areas of nwell or
other conflicting type). This allows extresist to extract the
entire substrate as a resistive network. The result is ugly and
may warrant some aggressive network simplification, but it should
at least be realistic.
2-terminal devices without complaining. The previous handling
seemed to be technically correct other than spitting out warnings
about missing terminals.
this limited ports to 16384, which seemed reasonable at the time.
However, the sky130_sram_macro layouts connect power and ground in a
way that when coupled with "extract unique" can generate tens of
thousands of ports and overrun the bit field, showing that automation
can do the unexpected. The solution was to split out the port number
from the label record as its own 32-bit value.
messages which was traced to code that changes a drivepoint position
to match a label; the same drivepoint may be part of the record for
the initial position to search on the net, in which case if the
position is changed, then the tile type needs to be changed to match
the new position.
using qsort() instead of its own linked-list-based sorting, which
is horribly inefficient. This change allows power nets (which
tend to be connected to all transistors) to be extracted in a
reasonable amount of time (hours instead of days).
an optional extra argument to the "select" command that can be used
to select labels by glob-style matching; e.g., "select area labels
VSS*" or "select less area labels *_1". This will help in managing
labels after flattening a standard cell design; e.g., by using
"select less area labels */VDD".
specific nets to extract, rather than excluding them. That allows
"extresist" to target specific nets like the power supply or a clock
tree for extraction.
this appears to work correctly but does not yet handle the implicit
substrate (space as substrate) or "virtually" isolated substrate regions
(which need to be removed for full parasitic extraction).
actually an issue and probably never relevant. extresist now works
except for substrate connections and soft connections between substrate
regions. That will require additional coding, not bugfixing, so I'm
committing the last of this set of bugfixes before starting that.
text formatting. Made one critical correction to ResGetDevice() to
pass the device type; otherwise, devices on different planes (e.g.,
MiM caps) with the same coordinate will always return the device on
the lowest plane, leading to incorrect results and an eventual crash
when the device record is free'd twice.
support of devices with terminals on different plances, such as
capacitors, diodes, and bipolar transistors. Output now appears
to give meaningful results for flattened layouts, although
numerous issues remain for hierarchical layouts.
the last commit, unfortunately. Thanks to Matt Guthaus for alerting me
to this. Also updated parts of the extresist code that remove the
dependence on ResConDCS; this is a minor update and should not affect
the operation of extresist. It is preparatory to doing more work to
support additional device types like capacitors, bipolars, and diodes.
code from extflat from type unsigned long to type TileTypeBitMask.
This increases the number of types of each to 256 and tracks the
number of types, so it should be difficult to exceed this amount.
recursive loop and crash magic. Corrected a number of other issues
along the way, especially one where routines in EFantenna and extresist
make use of array EFDevTypes which was only created by ext2sim and
ext2spice, and freed when done. Having run extresist through valgrind,
there are still issues in the code.
commit, mostly relating to the scale of values in the ".nodes" file
produced by ext2sim. Making this file CIF syntax seemed unnecessary,
so I removed the CIF syntax and scaling. "extresist" can now produce
an apparently valid output on a standard cell layout. Even with the
change, the extresist output is still only pseudo-hierarchical, so
this does not preclude the need for eliminating the .sim format file
in favor of the .ext file, but it provides a working intermediate
form.
types and substrate connections. This is an intermediate step to
switching from a sim file format to an ext file format for input,
but resolves the worst issues of having the sim file not recognize
the devices or the substrate nodes. Implemented by using the sim
subcircuit format introduced in IRSIM with the "user subcircuit"
package. Implementation unfinished (work in progress).
a long-standing error (introduced with the "extresist geometry"
option) that can cause nets not to be extracted (due to the first
record not having extraction data, which was itself a long-standing
error in the code but which was not fixed correctly); (2) handle
"device mosfet" type transistors (previously only handled the old
"fet" type extraction devices); and (3) correct for the res.ext
file having a different scalefactor relative to the .ext file. The
latter item was solved by forcing all input to scale like
ExtCurStyle->exts_unitsPerLambda, locally correcting all input as
needed. Note that extresist still needs to handle other extraction
devices (e.g., resistors and capacitors) but those will require
additional handling in the routines which analyze the current path
to determine how to break up wires into paths.
simple FET device in extresist. Also: Extended the bloat-all CIF operator
again, allowing the trigger layer for the bloat operation to include both
CIF layers and magic layers (previously only magic layers were supported).
This extension is possible due to the previous extension allowing the
trigger layer and bloating layers to be on separate planes. This operator
extension is useful for tagging geometry that is in the proximity of, but
not overlapping, geometry on another plane.
Darryl L. Miles
Tim Edwards