"csubcircuit" but swaps the first two pins (with the device
identifier layer becoming the 2nd pin and the other terminal the
first), which is needed for n-type diodes modeled as subcircuits
where the subcircuit pin order matches the order of pins for a
SPICE n-type diode component. Previously "msubcircuit" was used
for this purpose, but will calculate the wrong L and W. While
use of L and W for diodes is rare, this device type also works for
reversed capacitors (where the bottom or non-identifying layer
terminal is in the first pin position of the subcircuit).
version 8.3.521 that, due to an argument size mismatch, causes
device parameters in netlist output to be printed as zero.
Also added a small extension to the list of extraction types
to include "device veriloga", which has the same syntax as
"device subcircuit" but generates a component type "N"
(Verilog-A component) in the netlist output.
This has a knock on effect of causing EFvisit.c to require database.h
to be defined BEFORE the EFint.h due to an identical copy of ArrayInfo
type being present in both files.
Maybe there should be database_arrayinfo.h ? To remove the copy.
with "extract do local" now being equivalent to "extract path .".
This allows extraction files to be put in a subdirectory and not
clog up the current working directory. Also: Fixed some behavior
around the use of "ext2spice -p <path>" so that it (1) works, and
(2) is compatible with the new "extract path". Since the ext2spice
and ext2sim commands are effectively independent of the primary
extraction, the "-p" option is needed to correspond to the use of
"extract path". Hopefully this is seen as only a minor inconvenience.
This commit makes the code (mostly) C99-compatible, enabling to compile
it without the -Wno-error=implicit-function-declaration flag. This
way, Magic becomes usable on arm64 architectures, specifically on Apple
computers with M1/M2 SoC.
reading GDS files, caused by an unneeded change to pass both
the "original" filename and the actual filename when handling
compressed files---The original filename is unneeded.
(2) Implemented several new methods for parasitic extraction. The
first is an option offset value to apply to sidewall calculations.
This handles issues where actual wire separation is different
from drawn wire separation, which can be significant for the
1/d calculation of sidewall coupling. The second method is to
use the recently-added fringe halo to compute the coupling of the
fringe capacitance to nearby wires. Prior to this change, all
fringe capacitance was applied to surfaces directly under a wire
edge as if the fringe capacitance did not extend outward from the
edge. Now the capacitance is properly pro-rated for the position
of any overlapped shape inside the fringing field. Finally, the
third method added is a new search algorithm for finding the
nearest shapes along the length of a boundary. This is used for
sidewall coupling and fringe shielding, where the nearest shape
dominates the coupling, and any shapes behind are shielded and
may (to first order) be ignored. Previously, the entire halo
was searched without regard to shapes shielding other shapes
behind, and a recent correction added an ad-hoc search for
blocking shapes that was inefficient and not always correct.
The new method is both efficient and accurate.
fact that "extract all" does not enumerate cells from bottom up
as I had assumed---The order is roughly bottom-to-top, but cells
re-used in different places in the hierarchy could end up called
before one or more of their own subcells is extracted. Since
this conflicted with the preparation of the substrate in each
extracted subcircuit, I changed the method to enumerate cells so
that it is properly bottom-to-top. Also, methods were added to
"extract" (incremental), "extract cell", and "extract parents"
to ensure that the substrate is prepared on all subcells before
extraction.
a routine that should have been called with a NULL argument, but
instead was called with no argument, making the behavior system-
dependent. Revised the parsing of the "defaultareacap" and
"defaultperimeter" statements in the tech file, such that the short
version of both statements gets automatic handling of the substrate
and isolated substrate areas; this goes back to the recent change
in extraction behavior to redefine the "substrate type" (e.g., pwell)
during extraction as defining isolated substrate areas, and not the
default substrate. The earlier code change dealt with problems
related to extracting nodes and regions, but did not consider how
parasitic capacitance was affected. This commit resolves that issue.
statements in the .ext file output to those that mark a port as
equivalent to the node name used elsewhere in the file. This
limits unnecessary output of "equiv" statements that can bog down
ext2spice and other commands that use the .ext file contents.
implements a method for handling ports in a subcircuit that have different
port names and indexes but are shorted together. "none" is the default
and backwards-compatible behavior that merges ports together, which will
often cause one of the ports to be optimized out of the netlist. "resistor"
will separate the port names with a 0-ohm ideal resistor. "voltage" will
separate the port names with a 0-volt voltage source. This should work
well for simulation and potentially for LVS, although its impact on LVS
has not been fully investigated.
for sticky labels making connections through the hierarchy. This
is only needed for some annoying layouts that put point-size labels
with no connecting geometry in cells, and causes magic to spent
excessive amounts of time searching through labels for any layout
that has lots of labels.
not restored until after all cells have been processed through
extraction. Otherwise, top-down connections can end up with
different generated names for the same node, resulting in a
disconnect in the netlist.
areas and writes ANTENNAGATEAREA and ANTENNADIFFAREA values.
(2) Determines "USE POWER" or "USE GROUND" from label names
matching Tcl variables $VDD and $GND, if the USE has not been
registered as a cell property (knowning the use allows magic
to avoid writing an ANTENNADIFFAREA for power rails, although
doing so should not be an issue).
checks. Added new command "antennacheck" and a routine that
adds feedback entries where violations are found. Extended the
syntax of the extraction section of the techfile to support the
antenna ratios and antenna calculation methods.
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
R. Timothy Edwards
Darryl L. Miles
Alessandro De Laurenzis