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112 Commits

Author SHA1 Message Date
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein bdb8a7bcc2 WIP: reverted modifications on SPICE reader. 2019-07-08 21:51:59 +02:00
Matthias Koefferlein 9625caea65 WIP: added full LVS test. 2019-07-08 21:43:06 +02:00
Matthias Koefferlein b48453633f WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
Matthias Koefferlein bc2d9448d6 Providing LVS tests. 2019-07-07 21:33:28 +02:00
Matthias Koefferlein 95a1e38fe3 WIP: better reproducablility for .lvsdb layer names, updated tests. 2019-07-07 19:39:00 +02:00
Matthias Koefferlein 0595ec2e0f WIP: one more test for LVS 2019-07-06 09:08:32 +02:00
Matthias Koefferlein 2f6aae7204 WIP: refactoring, added first tests for LVS 2019-07-06 08:52:40 +02:00
Matthias Koefferlein 8aa6f4edcf WIP: added more test data, doc links 2019-07-02 02:03:58 +02:00
Matthias Koefferlein ae71356052 Added reference circuit 2019-07-02 00:30:50 +02:00
Matthias Koefferlein 5bfed544b7 Added inverter test layout 2019-07-02 00:27:05 +02:00
Matthias Koefferlein 9f26553d4b Added inverter test layout 2019-07-02 00:25:31 +02:00