* First step for solution:
Problem was: the ambiguity resolver was making decisions which later resulted in
a name conflict. Later on, another branch of the backtracking algorithm came
across the same situation but decided based on names, creating an conflict.
First part of the solution is to establish the backtracking information
during ambiguity resolution and using that rather than an alternative branch
later on. This avoids this conflict, but does not favor names as mandated
by the "use_names" flag. This will be the second step of the solution.
* Bugfixed solution (partially)
* Introducing third pass in netlist compare
The second pass is "ambiguity resolution by name" and
is skipped if "consider_net_names" is false. The third
pass then is ignoring the names.
* Bugfix
* Comment fixed, test updates
* Added tests
* Added test data variant for CentOS 8
* Providing a "refresh" function for triggering a refresh from inside the lib
Some other glitches were fixed too:
* LibraryManager wasn't thread-safe
* Library destructor wasn't unregistering
* Crash when re-registering the same library again
* In LibrariesTest normalization of layouts must not include
re-creation of library references to avoid side effects.
Save without context.
* Added missing files
* Fixed unit tests.
Fixed some more glitches while doing so:
* cell.name (gsi) was giving "basic_name", now it's changed to the
internal name to be consistent with "name=". The "functional name"
is still available as "basic_name".
* The basic name was rendering "<defunct>..." for defunct cells
and has been changed to the functional name. Otherwise this
is not accessible.
The bug was that while iterating a Region during the gate traversal,
the "select_interacting" was triggering a sort() which changed the
order.
Solution is to pre-sort when iterators are issued also when the
iterator is non-region selecting. This way, plain and region query
iterators can be used together. In addition, the dirty flag scheme
of Cell+Shapes was cleaned up a little for bboxes.
Basic change: DeepShapeStore+CellMapping uses (new) hier_generation_id of Layout to figure out
if the hierarchy has changed and the cache needs update.
1. Be more careful with net names
Net names are used now for sorting the graph nodes, but not for
strict compare. This is useful to derive swappable pins for
blackbox circuits.
2. Be more careful with pins from schematic netlist
Pins from schematic netlist without a corresponding pin on the layer
side are treated as mandatory unless connected to a trivial net.
Pins connecting to non-trivial nets inside the subcircuit are always
considered mandatory.
This way schematic pins enforce corresponding layout pins.
On the other hand, layout pins connecting to trivial nets inside
the subcircuit are considered non-mandatory.
1. removed some duplicate symbol linker error
2. removed many compiler warnings (mainly size_t/int compatibility)
3. consistent definition of db::pcell_id_type
4. removed UTF-8 character codes from string constants
5. float constants for float arguments
6. timeout in tlHttp when no openssl lib is found (instead of stalling
app)
While doing so changed the following things too:
- Instance and Shapes methods raise an exception if not
in editable mode and with undo/redo
- Faster and leaner undo/redo on Shapes#clear
Previously: matching of blackbox pins was enforced
by using pin names for passive nets in the compare.
Problem: no match was achieved when pins are not
named or not named consistently.
In this case, it's desirable to treat them as
ambiguous.
The new solution is to let the ambiguity resolver handle
that using an extended definition of the net names:
it will take the pin name into account if an unnamed net
is attached to a pin.
In addition, net ambiguities are projected to pin
equivalence now. This also will propagate symmetry
through nested blocks (dbNetlistCompareTests:20_BusLikeConnections).
Abstract pins are created when pins are not attached to any or only to passive nets
(passive nets are those without device terminals or subcircuit pins).
1. Such pins were treated swappable. Now named pins will not be treated
swappable but are mapped by name. This enables blackbox models where
the pins are labelled and must correspond to schematic pins.
2. A bug was present which lead to incorrect handling of abstract
nets in net compare.
Matthias Köfferlein
klayoutmatthias