mirror of https://github.com/KLayout/klayout.git
Merge pull request #862 from KLayout/matching-of-blackbox-circuits
Enhanced matching of blackbox/pin ambiguities
This commit is contained in:
Matthias Köfferlein
GitHub
commit
19f2769137
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@ -94,11 +94,43 @@ bool combined_case_sensitive (const db::Netlist *a, const db::Netlist *b)
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return csa && csb;
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}
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int name_compare (const db::Net *a, const db::Net *b)
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// --------------------------------------------------------------------------------------------------------------------
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// Net name compare
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// for comparing the net names also employ the pin name if one is given
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static const std::string &extended_net_name (const db::Net *n)
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{
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return db::Netlist::name_compare (combined_case_sensitive (a->netlist (), b->netlist ()), a->name (), b->name ());
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if (! n->name ().empty ()) {
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return n->name ();
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} else if (n->begin_pins () != n->end_pins ()) {
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return n->begin_pins ()->pin ()->name ();
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} else {
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return n->name ();
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}
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}
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int name_compare (const db::Net *a, const db::Net *b)
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{
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return db::Netlist::name_compare (combined_case_sensitive (a->netlist (), b->netlist ()), extended_net_name (a), extended_net_name (b));
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}
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static bool net_names_are_different (const db::Net *a, const db::Net *b)
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{
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if (! a || ! b || extended_net_name (a).empty () || extended_net_name (b).empty ()) {
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return false;
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} else {
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return name_compare (a, b) != 0;
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}
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}
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static bool net_names_are_equal (const db::Net *a, const db::Net *b)
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{
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if (! a || ! b || extended_net_name (a).empty () || extended_net_name (b).empty ()) {
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return false;
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} else {
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return name_compare (a, b) == 0;
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}
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}
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// --------------------------------------------------------------------------------------------------------------------
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// DeviceCompare definition and implementation
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@ -1466,17 +1498,7 @@ NetGraphNode::net_less (const db::Net *a, const db::Net *b)
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return (a != 0) < (b != 0);
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}
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if (a != 0) {
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if (a->pin_count () != b->pin_count ()) {
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return a->pin_count () < b->pin_count ();
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}
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if (a->pin_count () > 0) {
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const std::string &pna = a->begin_pins ()->pin ()->name ();
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const std::string &pnb = b->begin_pins ()->pin ()->name ();
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if (! pna.empty () && ! pnb.empty ()) {
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return db::Netlist::name_compare (combined_case_sensitive (a->netlist (), b->netlist ()), pna, pnb) < 0;
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}
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}
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return false;
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return a->pin_count () < b->pin_count ();
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} else {
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return false;
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}
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@ -1489,17 +1511,7 @@ NetGraphNode::edge_equal (const db::Net *a, const db::Net *b)
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return false;
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}
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if (a != 0) {
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if (a->pin_count () != b->pin_count ()) {
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return false;
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}
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if (a->pin_count () > 0) {
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const std::string &pna = a->begin_pins ()->pin ()->name ();
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const std::string &pnb = b->begin_pins ()->pin ()->name ();
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if (! pna.empty () && ! pnb.empty ()) {
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return db::Netlist::name_compare (combined_case_sensitive (a->netlist (), b->netlist ()), pna, pnb) == 0;
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}
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}
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return true;
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return a->pin_count () == b->pin_count ();
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} else {
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return true;
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}
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@ -2324,24 +2336,6 @@ static void sort_node_range_by_best_match (const NodeRange &nr)
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}
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}
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static bool net_names_are_different (const db::Net *a, const db::Net *b)
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{
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if (! a || ! b || a->name ().empty () || b->name ().empty ()) {
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return false;
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} else {
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return name_compare (a, b) != 0;
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}
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}
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static bool net_names_are_equal (const db::Net *a, const db::Net *b)
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{
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if (! a || ! b || a->name ().empty () || b->name ().empty ()) {
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return false;
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} else {
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return name_compare (a, b) == 0;
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}
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}
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size_t
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NetGraph::derive_node_identities_from_ambiguity_group (const NodeRange &nr, DeviceMapperForTargetNode &dm, DeviceMapperForTargetNode &dm_other, SubCircuitMapperForTargetNode &scm, SubCircuitMapperForTargetNode &scm_other, size_t depth, size_t n_branch, TentativeNodeMapping *tentative, CompareData *data)
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{
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@ -2391,8 +2385,13 @@ NetGraph::derive_node_identities_from_ambiguity_group (const NodeRange &nr, Devi
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std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::const_iterator i1 = *ii1;
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// use net names to resolve ambiguities or for passive nets
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// (Rationale for the latter: passive nets cannot be told apart topologically and are typical for blackbox models.
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// So the net name is the only differentiator)
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bool use_name = ! data->dont_consider_net_names || i1->first->net ()->is_passive ();
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// in tentative mode, reject this choice if nets are named and all other nets in the ambiguity group differ -> this favors net matching by name
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if (! data->dont_consider_net_names && tentative) {
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if (use_name && tentative) {
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bool any_matching = false;
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for (std::vector<std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::const_iterator>::iterator ii2 = iters2.begin (); ii2 != iters2.end () && ! any_matching; ++ii2) {
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@ -2431,7 +2430,7 @@ NetGraph::derive_node_identities_from_ambiguity_group (const NodeRange &nr, Devi
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continue;
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}
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if (! data->dont_consider_net_names && net_names_are_equal (i1->first->net (), i2->first->net ())) {
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if (use_name && net_names_are_equal (i1->first->net (), i2->first->net ())) {
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if (options ()->debug_netcompare) {
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tl::info << indent_s << "=> accepted for identical names";
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@ -2525,6 +2524,9 @@ NetGraph::derive_node_identities_from_ambiguity_group (const NodeRange &nr, Devi
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// issue the matching pairs
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// ambiguous pins
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std::vector<size_t> pa, pb;
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for (std::vector<std::pair<const NetGraphNode *, const NetGraphNode *> >::const_iterator p = pairs.begin (); p != pairs.end (); ++p) {
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size_t ni = node_index_for_net (p->first->net ());
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@ -2532,27 +2534,43 @@ NetGraph::derive_node_identities_from_ambiguity_group (const NodeRange &nr, Devi
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TentativeNodeMapping::map_pair (0, this, ni, data->other, other_ni, dm, dm_other, *data->device_equivalence, scm, scm_other, *data->subcircuit_equivalence, depth);
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bool ambiguous = equivalent_other_nodes.has_attribute (p->second);
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if (options ()->debug_netcompare) {
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if (equivalent_other_nodes.has_attribute (p->second)) {
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if (ambiguous) {
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tl::info << indent_s << "deduced ambiguous match: " << p->first->net ()->expanded_name () << " vs. " << p->second->net ()->expanded_name ();
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} else {
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tl::info << indent_s << "deduced match: " << p->first->net ()->expanded_name () << " vs. " << p->second->net ()->expanded_name ();
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}
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}
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if (data->logger) {
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bool ambiguous = equivalent_other_nodes.has_attribute (p->second);
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if (ambiguous) {
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if (ambiguous) {
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if (data->logger) {
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data->logger->match_ambiguous_nets (p->first->net (), p->second->net ());
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} else {
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data->logger->match_nets (p->first->net (), p->second->net ());
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}
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for (db::Net::const_pin_iterator i = p->first->net ()->begin_pins (); i != p->first->net ()->end_pins (); ++i) {
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pa.push_back (i->pin ()->id ());
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}
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for (db::Net::const_pin_iterator i = p->second->net ()->begin_pins (); i != p->second->net ()->end_pins (); ++i) {
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pb.push_back (i->pin ()->id ());
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}
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} else if (data->logger) {
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data->logger->match_nets (p->first->net (), p->second->net ());
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}
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++*data->progress;
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}
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// marks pins on ambiguous nets as swappable
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if (! pa.empty ()) {
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data->circuit_pin_mapper->map_pins (circuit (), pa);
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}
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if (! pb.empty ()) {
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data->circuit_pin_mapper->map_pins (data->other->circuit (), pb);
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}
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// And seek further from these pairs
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for (std::vector<std::pair<const NetGraphNode *, const NetGraphNode *> >::const_iterator p = pairs.begin (); p != pairs.end (); ++p) {
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@ -24,6 +24,7 @@
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#include "dbNetlistDeviceClasses.h"
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#include "dbNetlistCompare.h"
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#include "dbNetlistCrossReference.h"
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#include "dbNetlistSpiceReader.h"
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class NetlistCompareTestLogger
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: public db::NetlistCompareLogger
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@ -2317,7 +2318,7 @@ TEST(15_EmptySubCircuitTest)
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" subcircuit TRANS $3 (G=OUT,S=$5,D=$2);\n"
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" subcircuit TRANS $4 (G=OUT,S=$4,D=$2);\n"
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"end;\n"
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// This circuit is an abstract and it's pins are defined by the pin names
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// This circuit is an abstract and its pins are defined by the pin names
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"circuit TRANS (G=$1,S=$2,D=$3);\n"
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"end;\n";
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@ -3540,22 +3541,22 @@ TEST(20_BusLikeConnections)
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"begin_circuit INV8_WRAP INV8_WRAP\n"
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"match_nets VSS VSS\n"
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"match_nets VDD VDD\n"
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"match_nets IN8 A8\n"
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"match_nets OUT8 Q8\n"
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"match_nets IN7 A7\n"
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"match_nets OUT7 Q7\n"
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"match_nets IN6 A6\n"
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"match_nets OUT6 Q6\n"
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"match_nets IN5 A5\n"
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"match_nets OUT5 Q5\n"
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"match_nets IN4 A4\n"
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"match_nets OUT4 Q4\n"
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"match_nets IN3 A3\n"
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"match_nets OUT3 Q3\n"
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"match_nets IN2 A2\n"
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"match_nets OUT2 Q2\n"
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"match_nets IN1 A1\n"
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"match_nets OUT1 Q1\n"
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"match_ambiguous_nets IN1 A1\n"
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"match_ambiguous_nets IN2 A2\n"
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"match_ambiguous_nets IN3 A3\n"
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"match_ambiguous_nets IN4 A4\n"
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"match_ambiguous_nets IN5 A5\n"
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"match_ambiguous_nets IN6 A6\n"
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"match_ambiguous_nets IN7 A7\n"
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"match_ambiguous_nets IN8 A8\n"
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"match_pins IN1 A1\n"
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"match_pins OUT1 Q1\n"
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"match_pins IN2 A2\n"
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@ -3579,22 +3580,22 @@ TEST(20_BusLikeConnections)
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"begin_circuit TOP TOP\n"
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"match_nets VSS VSS\n"
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"match_nets VDD VDD\n"
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"match_nets IN8 A8\n"
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"match_nets OUT8 Q8\n"
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"match_nets IN7 A7\n"
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"match_nets OUT7 Q7\n"
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"match_nets IN6 A6\n"
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"match_nets OUT6 Q6\n"
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"match_nets IN5 A5\n"
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"match_nets OUT5 Q5\n"
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"match_nets IN4 A4\n"
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"match_nets OUT4 Q4\n"
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"match_nets IN3 A3\n"
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"match_nets OUT3 Q3\n"
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"match_nets IN2 A2\n"
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"match_nets OUT2 Q2\n"
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"match_nets IN1 A1\n"
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"match_nets OUT1 Q1\n"
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"match_ambiguous_nets IN1 A1\n"
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"match_ambiguous_nets IN2 A2\n"
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"match_ambiguous_nets IN3 A3\n"
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"match_ambiguous_nets IN4 A4\n"
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"match_ambiguous_nets IN5 A5\n"
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"match_ambiguous_nets IN6 A6\n"
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"match_ambiguous_nets IN7 A7\n"
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"match_ambiguous_nets IN8 A8\n"
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"match_pins IN1 A1\n"
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"match_pins OUT1 Q1\n"
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"match_pins IN2 A2\n"
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@ -3687,22 +3688,22 @@ TEST(20_BusLikeConnections)
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"begin_circuit INV8_WRAP INV8_WRAP\n"
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"match_nets VSS VSS\n"
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"match_nets VDD VDD\n"
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"match_nets IN8 A8\n"
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"match_nets OUT8 Q8\n"
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"match_nets IN7 A7\n"
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"match_nets OUT7 Q7\n"
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"match_nets IN6 A6\n"
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"match_nets OUT6 Q6\n"
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"match_nets IN5 A5\n"
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"match_nets OUT5 Q5\n"
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"match_nets IN4 A4\n"
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"match_nets OUT4 Q4\n"
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"match_nets IN3 A3\n"
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"match_nets OUT3 Q3\n"
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"match_nets IN2 A2\n"
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"match_nets OUT2 Q2\n"
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"match_nets IN1 A1\n"
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"match_nets OUT1 Q1\n"
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"match_ambiguous_nets IN1 A1\n"
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"match_ambiguous_nets IN2 A2\n"
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"match_ambiguous_nets IN3 A3\n"
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"match_ambiguous_nets IN4 A4\n"
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"match_ambiguous_nets IN5 A5\n"
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"match_ambiguous_nets IN6 A6\n"
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"match_ambiguous_nets IN7 A7\n"
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"match_ambiguous_nets IN8 A8\n"
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"match_pins IN1 A1\n"
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"match_pins OUT1 Q1\n"
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"match_pins IN2 A2\n"
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@ -3726,22 +3727,22 @@ TEST(20_BusLikeConnections)
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"begin_circuit TOP TOP\n"
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"match_nets VSS VSS\n"
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"match_nets VDD VDD\n"
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"match_nets IN8 A8\n"
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"match_nets OUT8 Q8\n"
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"match_nets IN7 A7\n"
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"match_nets OUT7 Q7\n"
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"match_nets IN6 A6\n"
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"match_nets OUT6 Q6\n"
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"match_nets IN5 A5\n"
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"match_nets OUT5 Q5\n"
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"match_nets IN4 A4\n"
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"match_nets OUT4 Q4\n"
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"match_nets IN3 A3\n"
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"match_nets OUT3 Q3\n"
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"match_nets IN2 A2\n"
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"match_nets OUT2 Q2\n"
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"match_nets IN1 A1\n"
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"match_nets OUT1 Q1\n"
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"match_ambiguous_nets IN1 A1\n"
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"match_ambiguous_nets IN2 A2\n"
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"match_ambiguous_nets IN3 A3\n"
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"match_ambiguous_nets IN4 A4\n"
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"match_ambiguous_nets IN5 A5\n"
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"match_ambiguous_nets IN6 A6\n"
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"match_ambiguous_nets IN7 A7\n"
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"match_ambiguous_nets IN8 A8\n"
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"match_pins IN1 A1\n"
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"match_pins OUT1 Q1\n"
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"match_pins IN2 A2\n"
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@ -4560,3 +4561,20 @@ TEST(28_JoinSymmetricNets)
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)
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}
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TEST(29_EmptySubCircuitsFromSPICE)
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{
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db::Netlist a, b, c;
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tl::InputStream fa (tl::testdata () + "/algo/nl_compare_29_a.cir");
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tl::InputStream fb (tl::testdata () + "/algo/nl_compare_29_b.cir");
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tl::InputStream fc (tl::testdata () + "/algo/nl_compare_29_c.cir");
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db::NetlistSpiceReader reader;
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reader.read (fa, a);
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reader.read (fb, b);
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reader.read (fc, c);
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db::NetlistComparer comp;
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EXPECT_EQ (comp.compare (&a, &b), true);
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EXPECT_EQ (comp.compare (&a, &c), false);
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}
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@ -0,0 +1,130 @@
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* RINGO netlist before simplification
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* cell RINGO
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.SUBCKT RINGO
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* net 11 FB
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* net 12 VDD
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* net 15 OUT
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* net 16 ENABLE
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* net 19 BULK,VSS
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* cell instance $1 r0 *1 1.8,0
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X$1 12 1 19 12 11 16 19 ND2X1
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* cell instance $2 r0 *1 4.2,0
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X$2 12 2 19 12 1 19 INVX1
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* cell instance $3 r0 *1 6,0
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X$3 12 3 19 12 2 19 INVX1
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* cell instance $4 r0 *1 7.8,0
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X$4 12 4 19 12 3 19 INVX1
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* cell instance $5 r0 *1 9.6,0
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X$5 12 5 19 12 4 19 INVX1
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* cell instance $6 r0 *1 11.4,0
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X$6 12 6 19 12 5 19 INVX1
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* cell instance $7 r0 *1 13.2,0
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X$7 12 7 19 12 6 19 INVX1
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* cell instance $8 r0 *1 15,0
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X$8 12 8 19 12 7 19 INVX1
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* cell instance $9 r0 *1 16.8,0
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X$9 12 9 19 12 8 19 INVX1
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* cell instance $10 r0 *1 18.6,0
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X$10 12 10 19 12 9 19 INVX1
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* cell instance $11 r0 *1 20.4,0
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X$11 12 11 19 12 10 19 INVX1
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* cell instance $12 r0 *1 22.2,0
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X$12 12 15 19 12 11 19 INVX1
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* cell instance $13 r0 *1 3.28,4
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X$13 11 M1M2
|
||||
* cell instance $14 r0 *1 21.42,4
|
||||
X$14 11 M1M2
|
||||
* cell instance $15 r0 *1 0.6,0
|
||||
X$15 12 19 TIE
|
||||
* cell instance $16 r0 *1 0,0
|
||||
X$16 12 19 12 EMPTY
|
||||
* cell instance $17 r0 *1 24,0
|
||||
X$17 12 19 TIE
|
||||
* cell instance $18 r0 *1 25.2,0
|
||||
X$18 12 19 12 EMPTY
|
||||
* cell instance $19 r0 *1 23.6,4
|
||||
X$19 15 M1M2
|
||||
* cell instance $20 r0 *1 2.6,3.1
|
||||
X$20 16 M1M2
|
||||
.ENDS RINGO
|
||||
|
||||
* cell ND2X1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin B
|
||||
* pin A
|
||||
* pin BULK
|
||||
.SUBCKT ND2X1 1 2 3 4 5 6 9
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 B
|
||||
* net 6 A
|
||||
* net 9 BULK
|
||||
* cell instance $1 r0 *1 0.3,5.05
|
||||
X$1 6 1 2 PMOS3
|
||||
* cell instance $2 r0 *1 1,5.05
|
||||
X$2 5 2 1 PMOS3
|
||||
* cell instance $3 r0 *1 1,1.66
|
||||
X$3 5 2 10 NMOS2
|
||||
* cell instance $4 r0 *1 0.3,1.66
|
||||
X$4 6 10 3 NMOS2
|
||||
* cell instance $5 r0 *1 1.48,4
|
||||
X$5 5 POLYM1
|
||||
* cell instance $6 r0 *1 0.8,3.1
|
||||
X$6 6 POLYM1
|
||||
* device instance $1 0.85,5.8 LVPMOS
|
||||
M$1 2 6 1 4 LVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 1.55,5.8 LVPMOS
|
||||
M$2 1 5 2 4 LVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 0.85,2.135 LVNMOS
|
||||
M$3 3 6 10 9 LVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 1.55,2.135 LVNMOS
|
||||
M$4 10 5 2 9 LVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
||||
* cell INVX1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin IN
|
||||
* pin BULK
|
||||
.SUBCKT INVX1 1 2 3 4 5 7
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 IN
|
||||
* net 7 BULK
|
||||
* cell instance $1 r0 *1 0.3,5.05
|
||||
X$1 5 1 2 PMOS3
|
||||
* cell instance $2 r0 *1 0.3,1.66
|
||||
X$2 5 2 3 NMOS2
|
||||
* cell instance $3 r0 *1 0.6,3.1
|
||||
X$3 5 POLYM1
|
||||
* device instance $1 0.85,5.8 LVPMOS
|
||||
M$1 1 5 2 4 LVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 0.85,2.135 LVNMOS
|
||||
M$2 3 5 2 7 LVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT M1M2 $1
|
||||
.ENDS M1M2
|
||||
|
||||
.SUBCKT TIE $1 $2
|
||||
.ENDS TIE
|
||||
|
||||
.SUBCKT EMPTY $1 $2 $3
|
||||
.ENDS EMPTY
|
||||
|
||||
.SUBCKT POLYM1 $1
|
||||
.ENDS POLYM1
|
||||
|
||||
.SUBCKT NMOS2 $1 $2 $3
|
||||
.ENDS NMOS2
|
||||
|
||||
.SUBCKT PMOS3 $1 $2 $3
|
||||
.ENDS PMOS3
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
* RINGO netlist before simplification
|
||||
|
||||
* cell RINGO
|
||||
.SUBCKT RINGO
|
||||
* net 11 FB
|
||||
* net 12 VDD
|
||||
* net 15 OUT
|
||||
* net 16 ENABLE
|
||||
* net 19 BULK,VSS
|
||||
* cell instance $1 r0 *1 1.8,0
|
||||
X$1 12 1 19 12 11 16 19 ND2X1
|
||||
* cell instance $2 r0 *1 4.2,0
|
||||
X$2 12 2 19 12 1 19 INVX1
|
||||
* cell instance $3 r0 *1 6,0
|
||||
X$3 12 3 19 12 2 19 INVX1
|
||||
* cell instance $4 r0 *1 7.8,0
|
||||
X$4 12 4 19 12 3 19 INVX1
|
||||
* cell instance $5 r0 *1 9.6,0
|
||||
X$5 12 5 19 12 4 19 INVX1
|
||||
* cell instance $6 r0 *1 11.4,0
|
||||
X$6 12 6 19 12 5 19 INVX1
|
||||
* cell instance $7 r0 *1 13.2,0
|
||||
X$7 12 7 19 12 6 19 INVX1
|
||||
* cell instance $8 r0 *1 15,0
|
||||
X$8 12 8 19 12 7 19 INVX1
|
||||
* cell instance $9 r0 *1 16.8,0
|
||||
X$9 12 9 19 12 8 19 INVX1
|
||||
* cell instance $10 r0 *1 18.6,0
|
||||
X$10 12 10 19 12 9 19 INVX1
|
||||
* cell instance $11 r0 *1 20.4,0
|
||||
X$11 12 11 19 12 10 19 INVX1
|
||||
* cell instance $12 r0 *1 22.2,0
|
||||
X$12 12 15 19 12 11 19 INVX1
|
||||
* cell instance $13 r0 *1 3.28,4
|
||||
X$13 11 M1M2
|
||||
* cell instance $14 r0 *1 21.42,4
|
||||
X$14 11 M1M2
|
||||
* cell instance $15 r0 *1 0.6,0
|
||||
X$15 12 19 TIE
|
||||
* cell instance $16 r0 *1 0,0
|
||||
X$16 12 19 12 EMPTY
|
||||
* cell instance $17 r0 *1 24,0
|
||||
X$17 12 19 TIE
|
||||
* cell instance $18 r0 *1 25.2,0
|
||||
X$18 12 19 12 EMPTY
|
||||
* cell instance $19 r0 *1 23.6,4
|
||||
X$19 15 M1M2
|
||||
* cell instance $20 r0 *1 2.6,3.1
|
||||
X$20 16 M1M2
|
||||
.ENDS RINGO
|
||||
|
||||
* cell ND2X1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin B
|
||||
* pin A
|
||||
* pin BULK
|
||||
.SUBCKT ND2X1 1 2 3 4 5 6 9
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 B
|
||||
* net 6 A
|
||||
* net 9 BULK
|
||||
* cell instance $1 r0 *1 0.3,5.05
|
||||
X$1 6 1 2 PMOS3
|
||||
* cell instance $2 r0 *1 1,5.05
|
||||
X$2 5 2 1 PMOS3
|
||||
* cell instance $3 r0 *1 1,1.66
|
||||
X$3 5 2 10 NMOS2
|
||||
* cell instance $4 r0 *1 0.3,1.66
|
||||
X$4 6 10 3 NMOS2
|
||||
* cell instance $5 r0 *1 1.48,4
|
||||
X$5 5 POLYM1
|
||||
* cell instance $6 r0 *1 0.8,3.1
|
||||
X$6 6 POLYM1
|
||||
* device instance $1 0.85,5.8 LVPMOS
|
||||
M$1 2 6 1 4 LVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 1.55,5.8 LVPMOS
|
||||
M$2 1 5 2 4 LVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 0.85,2.135 LVNMOS
|
||||
M$3 3 6 10 9 LVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 1.55,2.135 LVNMOS
|
||||
M$4 10 5 2 9 LVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
||||
* cell INVX1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin IN
|
||||
* pin BULK
|
||||
.SUBCKT INVX1 1 2 3 4 5 7
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 IN
|
||||
* net 7 BULK
|
||||
* cell instance $1 r0 *1 0.3,5.05
|
||||
X$1 5 1 2 PMOS3
|
||||
* cell instance $2 r0 *1 0.3,1.66
|
||||
X$2 5 2 3 NMOS2
|
||||
* cell instance $3 r0 *1 0.6,3.1
|
||||
X$3 5 POLYM1
|
||||
* device instance $1 0.85,5.8 LVPMOS
|
||||
M$1 1 5 2 4 LVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 0.85,2.135 LVNMOS
|
||||
M$2 3 5 2 7 LVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT M1M2 $1
|
||||
.ENDS M1M2
|
||||
|
||||
.SUBCKT TIE $1 $2
|
||||
.ENDS TIE
|
||||
|
||||
.SUBCKT EMPTY $1 $2 $3
|
||||
.ENDS EMPTY
|
||||
|
||||
.SUBCKT POLYM1 $1
|
||||
.ENDS POLYM1
|
||||
|
||||
* different names than reference -> swapping of pins is possible
|
||||
.SUBCKT NMOS2 1 3 2
|
||||
.ENDS NMOS2
|
||||
|
||||
.SUBCKT PMOS3 $1 $2 $3
|
||||
.ENDS PMOS3
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
* RINGO netlist before simplification
|
||||
|
||||
* cell RINGO
|
||||
.SUBCKT RINGO
|
||||
* net 11 FB
|
||||
* net 12 VDD
|
||||
* net 15 OUT
|
||||
* net 16 ENABLE
|
||||
* net 19 BULK,VSS
|
||||
* cell instance $1 r0 *1 1.8,0
|
||||
X$1 12 1 19 12 11 16 19 ND2X1
|
||||
* cell instance $2 r0 *1 4.2,0
|
||||
X$2 12 2 19 12 1 19 INVX1
|
||||
* cell instance $3 r0 *1 6,0
|
||||
X$3 12 3 19 12 2 19 INVX1
|
||||
* cell instance $4 r0 *1 7.8,0
|
||||
X$4 12 4 19 12 3 19 INVX1
|
||||
* cell instance $5 r0 *1 9.6,0
|
||||
X$5 12 5 19 12 4 19 INVX1
|
||||
* cell instance $6 r0 *1 11.4,0
|
||||
X$6 12 6 19 12 5 19 INVX1
|
||||
* cell instance $7 r0 *1 13.2,0
|
||||
X$7 12 7 19 12 6 19 INVX1
|
||||
* cell instance $8 r0 *1 15,0
|
||||
X$8 12 8 19 12 7 19 INVX1
|
||||
* cell instance $9 r0 *1 16.8,0
|
||||
X$9 12 9 19 12 8 19 INVX1
|
||||
* cell instance $10 r0 *1 18.6,0
|
||||
X$10 12 10 19 12 9 19 INVX1
|
||||
* cell instance $11 r0 *1 20.4,0
|
||||
X$11 12 11 19 12 10 19 INVX1
|
||||
* cell instance $12 r0 *1 22.2,0
|
||||
X$12 12 15 19 12 11 19 INVX1
|
||||
* cell instance $13 r0 *1 3.28,4
|
||||
X$13 11 M1M2
|
||||
* cell instance $14 r0 *1 21.42,4
|
||||
X$14 11 M1M2
|
||||
* cell instance $15 r0 *1 0.6,0
|
||||
X$15 12 19 TIE
|
||||
* cell instance $16 r0 *1 0,0
|
||||
X$16 12 19 12 EMPTY
|
||||
* cell instance $17 r0 *1 24,0
|
||||
X$17 12 19 TIE
|
||||
* cell instance $18 r0 *1 25.2,0
|
||||
X$18 12 19 12 EMPTY
|
||||
* cell instance $19 r0 *1 23.6,4
|
||||
X$19 15 M1M2
|
||||
* cell instance $20 r0 *1 2.6,3.1
|
||||
X$20 16 M1M2
|
||||
.ENDS RINGO
|
||||
|
||||
* cell ND2X1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin B
|
||||
* pin A
|
||||
* pin BULK
|
||||
.SUBCKT ND2X1 1 2 3 4 5 6 9
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 B
|
||||
* net 6 A
|
||||
* net 9 BULK
|
||||
* cell instance $1 r0 *1 0.3,5.05
|
||||
X$1 6 1 2 PMOS3
|
||||
* cell instance $2 r0 *1 1,5.05
|
||||
X$2 5 2 1 PMOS3
|
||||
* cell instance $3 r0 *1 1,1.66
|
||||
X$3 5 2 10 NMOS2
|
||||
* cell instance $4 r0 *1 0.3,1.66
|
||||
X$4 6 10 3 NMOS2
|
||||
* cell instance $5 r0 *1 1.48,4
|
||||
X$5 5 POLYM1
|
||||
* cell instance $6 r0 *1 0.8,3.1
|
||||
X$6 6 POLYM1
|
||||
* device instance $1 0.85,5.8 LVPMOS
|
||||
M$1 2 6 1 4 LVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 1.55,5.8 LVPMOS
|
||||
M$2 1 5 2 4 LVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 0.85,2.135 LVNMOS
|
||||
M$3 3 6 10 9 LVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 1.55,2.135 LVNMOS
|
||||
M$4 10 5 2 9 LVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
||||
* cell INVX1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin IN
|
||||
* pin BULK
|
||||
.SUBCKT INVX1 1 2 3 4 5 7
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 IN
|
||||
* net 7 BULK
|
||||
* cell instance $1 r0 *1 0.3,5.05
|
||||
X$1 5 1 2 PMOS3
|
||||
* cell instance $2 r0 *1 0.3,1.66
|
||||
X$2 5 2 3 NMOS2
|
||||
* cell instance $3 r0 *1 0.6,3.1
|
||||
X$3 5 POLYM1
|
||||
* device instance $1 0.85,5.8 LVPMOS
|
||||
M$1 1 5 2 4 LVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 0.85,2.135 LVNMOS
|
||||
M$2 3 5 2 7 LVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT M1M2 $1
|
||||
.ENDS M1M2
|
||||
|
||||
.SUBCKT TIE $1 $2
|
||||
.ENDS TIE
|
||||
|
||||
.SUBCKT EMPTY $1 $2 $3
|
||||
.ENDS EMPTY
|
||||
|
||||
.SUBCKT POLYM1 $1
|
||||
.ENDS POLYM1
|
||||
|
||||
* same names than reference but swapped
|
||||
.SUBCKT NMOS2 $1 $3 $2
|
||||
.ENDS NMOS2
|
||||
|
||||
.SUBCKT PMOS3 $1 $2 $3
|
||||
.ENDS PMOS3
|
||||
|
|
@ -100,7 +100,7 @@ M$4 10 5 2 9 LVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
|||
* net 5 IN
|
||||
* net 7 BULK
|
||||
* cell instance $1 r0 *1 0.3,5.05
|
||||
X$1 5 2 1 PMOS3
|
||||
X$1 5 1 2 PMOS3
|
||||
* cell instance $2 r0 *1 0.3,1.66
|
||||
X$2 5 2 3 NMOS2
|
||||
* cell instance $3 r0 *1 0.6,3.1
|
||||
|
|
@ -111,41 +111,20 @@ M$1 1 5 2 4 LVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
|||
M$2 3 5 2 7 LVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell M1M2
|
||||
* pin
|
||||
.SUBCKT M1M2 1
|
||||
.SUBCKT M1M2 $1
|
||||
.ENDS M1M2
|
||||
|
||||
* cell TIE
|
||||
* pin VDD
|
||||
* pin BULK,VSS
|
||||
.SUBCKT TIE 1 2
|
||||
* net 1 VDD
|
||||
* net 2 BULK,VSS
|
||||
.SUBCKT TIE $1 $2
|
||||
.ENDS TIE
|
||||
|
||||
* cell EMPTY
|
||||
* pin
|
||||
* pin
|
||||
* pin
|
||||
.SUBCKT EMPTY 1 2 3
|
||||
.SUBCKT EMPTY $1 $2 $3
|
||||
.ENDS EMPTY
|
||||
|
||||
* cell POLYM1
|
||||
* pin
|
||||
.SUBCKT POLYM1 1
|
||||
.SUBCKT POLYM1 $1
|
||||
.ENDS POLYM1
|
||||
|
||||
* cell NMOS2
|
||||
* pin
|
||||
* pin
|
||||
* pin
|
||||
.SUBCKT NMOS2 1 2 3
|
||||
.SUBCKT NMOS2 $1 $2 $3
|
||||
.ENDS NMOS2
|
||||
|
||||
* cell PMOS3
|
||||
* pin
|
||||
* pin
|
||||
* pin
|
||||
.SUBCKT PMOS3 1 2 3
|
||||
.SUBCKT PMOS3 $1 $2 $3
|
||||
.ENDS PMOS3
|
||||
|
|
|
|||
Loading…
Reference in New Issue