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1361 Commits

Author SHA1 Message Date
Matthias Koefferlein 722b45b721 Fixed tests 2021-07-19 07:47:41 +02:00
Matthias Koefferlein bc74f189f8 Introducing asymmetric ambiguity groups for better matching of black box circuits with optional pins. 2021-07-18 23:33:01 +02:00
Matthias Koefferlein 70f4c7e2b5 A small refactoring. 2021-07-18 23:09:51 +02:00
Matthias Koefferlein 2c8d065eb3 Some enhancments + test update 
1. Be more careful with net names
Net names are used now for sorting the graph nodes, but not for
strict compare. This is useful to derive swappable pins for
blackbox circuits.

2. Be more careful with pins from schematic netlist
Pins from schematic netlist without a corresponding pin on the layer
side are treated as mandatory unless connected to a trivial net.
Pins connecting to non-trivial nets inside the subcircuit are always
considered mandatory.
This way schematic pins enforce corresponding layout pins.
On the other hand, layout pins connecting to trivial nets inside
the subcircuit are considered non-mandatory.
 2021-07-18 22:34:02 +02:00
Matthias Koefferlein 51d117e379 Refined black box pin heuristics 
Pins are required to match if they are passive inside the
subcircuit but connected to a non-trivial net in the calling circuit.
 2021-07-18 20:39:19 +02:00
Matthias Koefferlein 05386668b4 Re-introducing pin name mapping for net assignment 2021-07-18 20:20:23 +02:00
Matthias Koefferlein 23bea5dc07 Using real pin IDs for printing nodes in netlist compare debug output 2021-07-18 17:39:32 +02:00
Matthias Koefferlein d018805c23 Some refactoring. 2021-07-18 16:54:27 +02:00
Matthias Koefferlein 2f3e113db0 Added missing subcircuit mismatch events to netlist compare 2021-07-17 22:06:06 +02:00
Matthias Koefferlein 3f3f4c9173 Fixed some compiler warnings. 2021-07-17 22:03:22 +02:00
Matthias Köfferlein 054bfa3be4
Merge pull request #865 from KLayout/issue-864 
Fixed #864 (Shapes#copy_shapes does not support undo/redo)
 2021-07-17 13:44:15 +02:00
Matthias Köfferlein 19f2769137
Merge pull request #862 from KLayout/matching-of-blackbox-circuits 
Enhanced matching of blackbox/pin ambiguities
 2021-07-17 13:43:59 +02:00
klayoutmatthias 1555daf68c Adjustments for Windows build with MSVC2019 (VC 16.10.31419.357) 
1. removed some duplicate symbol linker error
2. removed many compiler warnings (mainly size_t/int compatibility)
3. consistent definition of db::pcell_id_type
4. removed UTF-8 character codes from string constants
5. float constants for float arguments
6. timeout in tlHttp when no openssl lib is found (instead of stalling
   app)
 2021-07-17 00:20:55 +02:00
Matthias Koefferlein 2fee924103 Updated the solution 2021-07-15 23:39:02 +02:00
Matthias Koefferlein d14892382c Fixed #864 (Shapes#copy_shapes does not support undo/redo) 
While doing so changed the following things too:
- Instance and Shapes methods raise an exception if not
  in editable mode and with undo/redo
- Faster and leaner undo/redo on Shapes#clear
 2021-07-15 00:44:28 +02:00
Matthias Koefferlein 2b447854f9 Enhanced matching of blackbox/pin ambiguities 
Previously: matching of blackbox pins was enforced
by using pin names for passive nets in the compare.
Problem: no match was achieved when pins are not
named or not named consistently.

In this case, it's desirable to treat them as
ambiguous.

The new solution is to let the ambiguity resolver handle
that using an extended definition of the net names:
it will take the pin name into account if an unnamed net
is attached to a pin.

In addition, net ambiguities are projected to pin
equivalence now. This also will propagate symmetry
through nested blocks (dbNetlistCompareTests:20_BusLikeConnections).
 2021-07-08 23:54:20 +02:00
Matthias Koefferlein bad3232415 Trying to fix a linker problem. 2021-07-07 08:03:07 +02:00
Matthias Koefferlein 4e54715d64 Merge branch 'wip-lvs' 2021-07-06 23:40:44 +02:00
Matthias Köfferlein e78d0d81ae
Merge pull request #849 from KLayout/lvs-blackbox 
Lvs blackbox
 2021-07-06 23:38:21 +02:00
Matthias Koefferlein 720057e071 Added a #include which was missing 2021-07-06 21:16:57 +02:00
Matthias Koefferlein 8f65ab099f Fixed DeviceClass assignment operator 2021-07-06 07:56:27 +02:00
Matthias Koefferlein 4e0d8d92ef Updated doc, reverted netlist writer to write all parameters - it will only write primary parameters for R, L and C 2021-07-05 22:45:40 +02:00
Matthias Koefferlein e34fc8967a Some enhancements 
* Device#net_for_terminal with terminal name
* Spice writer now dumps all parameters for resistors and caps (also secondary)
* Enabled Spice writer delegate in LVS (spice_format(...))
* Device class factories for built-in device extractors
 2021-07-05 22:22:13 +02:00
Matthias Koefferlein ba35ac9bfe Doc update, some tests 2021-07-05 21:06:02 +02:00
Matthias Koefferlein c62592ede1 Added test for device class factory. 2021-07-05 19:55:55 +02:00
Matthias Koefferlein 4303e1ab73 Revert change of making spice parameters primary - will create problems in swappable parameters such as AD and AS 2021-07-04 19:58:15 +02:00
Matthias Koefferlein ae6f77f45f Serialization of custom device classes 2021-07-04 19:14:37 +02:00
Matthias Koefferlein 3220bdf60d Added device class templates for CapWithBulk and ResWithBulk 2021-07-04 19:14:11 +02:00
Matthias Koefferlein ce61145f1c More control over primary/secondary flag of parameters in device extraction 
- Spice reader will set primary flag for all (known) parameters
  read from a Spice netlist
- "extract_devices" will return the device class object
- primary/secondary flag can be set on device class objects
  through "enable_devices"
 2021-07-04 17:05:17 +02:00
Matthias Koefferlein 1a0b05e663 Updated test data 2021-07-02 23:38:38 +02:00
Matthias Koefferlein 79c552b300 Fixed #858 (+ line continuation after blanks in Spice reader) 2021-07-02 23:31:54 +02:00
Matthias Koefferlein fd5efe9f92 Fixed #854 2021-07-02 00:46:22 +02:00
Matthias Koefferlein 6f63fa09bf Fixed #856 2021-07-02 00:44:17 +02:00
Matthias Koefferlein 3d6119f2a6 Updated tests, sloppy 'same_nets' in non-must-match mode 2021-06-29 08:43:28 +02:00
Matthias Koefferlein ab70c42c68 Some enhancements for strong matching of nets 
* same_nets! method for strong matching
* same_nets and same_nets! except glob pattern to circuits and nets
* both observe case sensitivity
* helper functions for case sensitivity Netlist#is_case_sensitive?, Netlist#case_sensitive=
* Netlist#nets_by_name to get nets from pattern
 2021-06-28 22:33:46 +02:00
Matthias Koefferlein 72dc94197e New method: Circuit#nets_by_name 2021-06-28 20:29:40 +02:00
Matthias Koefferlein e0ccb4f980 Fixed a typo 2021-06-28 18:57:09 +02:00
Matthias Koefferlein 24afd571f0 LVS: can be used anywhere now: tolerance and join_symmetric_nets 2021-06-28 18:56:07 +02:00
Matthias Koefferlein c24c0933bf Bugfix: blackbox mode/abstract pins 
Abstract pins are created when pins are not attached to any or only to passive nets
(passive nets are those without device terminals or subcircuit pins).

1. Such pins were treated swappable. Now named pins will not be treated
   swappable but are mapped by name. This enables blackbox models where
   the pins are labelled and must correspond to schematic pins.
2. A bug was present which lead to incorrect handling of abstract
   nets in net compare.
 2021-06-27 22:56:28 +02:00
Matthias Koefferlein d65148ed0b Fixed #846 2021-06-27 17:29:41 +02:00
Matthias Koefferlein 881e0010d5 Implemented with(out)_angle, with(out)_area on edge pairs (DRC, GSI). Deprecated 'with(out)_angle' on polygon layers (DRC) as this is now redundant with 'corners' 2021-06-27 14:18:04 +02:00
Matthias Koefferlein 5251520876 Added more filters for edge pairs: with_area, with_internal_angle. Added tests 2021-06-21 23:44:48 +02:00
Matthias Koefferlein 6e7c9192d4 Implemented #818 2021-06-20 21:45:51 +02:00
Matthias Koefferlein 2bbf6b6998 Merge branch 'clipped-25d-view' 2021-06-20 21:02:40 +02:00
Matthias Koefferlein 5fb2f024dc Fixed some typos 2021-06-19 23:12:59 +02:00
Matthias Koefferlein 71e290b50e Added test for the last commit 2021-06-13 23:02:53 +02:00
Matthias Koefferlein d1f38a36b1 Not directly related (initially so): EdgeProcessor can restart now. 2021-06-13 23:02:09 +02:00
Matthias Koefferlein 3b22bc0a42 Fixed the fix: considering the case of non-layout hosted Shapes container too 2021-06-12 23:34:32 +02:00
Matthias Koefferlein 115593575d Merge branch 'master' of github.com:KLayout/klayout into issue-835 2021-06-12 09:47:31 +02:00
Matthias Koefferlein 6f583b1b21 Fixed #835 2021-06-12 09:45:02 +02:00
Matthias Köfferlein 8bd58be534
Merge pull request #830 from KLayout/issue-824 
Issue 824
 2021-06-12 08:58:00 +02:00
Matthias Koefferlein 43c941004a Fixed embarrassing typo: Minkowsky -> Minkowski (Hermann Minkowski, 22 June 1864 – 12 January 1909) 2021-06-10 23:33:49 +02:00
Eugene Zelenko ed27447ce0 Fix misspellings in db. 2021-06-07 18:21:02 -07:00
Matthias Koefferlein 8b528a8a7a Refactored the compound op node cache for multithreading support 2021-06-07 22:46:15 +02:00
Matthias Koefferlein 02ec262df0 Normalized resistor contact polygons for better test reproducibility. 2021-06-03 23:43:00 +02:00
Matthias Koefferlein 7aaddcf205 Normalize S/D choice on MOS transistor extraction for better test reproducability 2021-06-03 17:32:38 +02:00
Matthias Koefferlein a762797d58 Typos fixed. 2021-06-01 21:32:24 +02:00
Matthias Koefferlein ef01bbf81b Restored merge behavior for DRC 'or' also in deep mode 2021-05-31 18:24:00 +02:00
Matthias Köfferlein 63f4d727e9
Merge pull request #813 from KLayout/wip 
Wip
 2021-05-29 23:59:44 +02:00
Matthias Koefferlein 83685a3715 Fixed a build issue. 2021-05-29 22:06:13 +02:00
Matthias Koefferlein eeaab8a417 Bugfix: Region#flatten and Edges#flatten did not update the merged cache to flat and Region#flatten did not produce PolygonRefs 2021-05-29 19:28:56 +02:00
Matthias Koefferlein 5ceeafc0ff Implemented #808 (Feature suggestion: DRC to report edges attached to corners as edge pairs). Solution is available for DRC layers and universal DRC expressions. 2021-05-29 17:57:38 +02:00
Matthias Koefferlein e57d573a42 Tests, so bug fixes, some refactoring 2021-05-29 09:43:12 +02:00
Matthias Koefferlein c8548709bb Implemented edge pair filters, DRC: with(out)_angle, with(out)_length and with(out)_distance 2021-05-28 23:46:52 +02:00
Matthias Koefferlein fcb966393a Fixed #806: first, the internal error gone. Second, the implementation of custom comparers is simplified as the 'equals' method does not need to be implemented. 2021-05-26 22:39:28 +02:00
Matthias Koefferlein ef22ead019 Fixed a bug in the Spice writer implementation (res3 not considered) 2021-05-26 22:27:42 +02:00
Niko Savola ff90c476c3 Fix typos systemically in gsiDecl*.cc 2021-05-26 13:18:23 +03:00
Niko Savola 99ef222f50
Fix more typos in gsiDeclDbLayoutToNetlist.cc 
\\make_incluidelayer -> \\make_includelayer
sqaure -> square
 2021-05-26 12:37:24 +03:00
Niko Savola b27e5de023
Fix typo in gsiDeclDbLayoutToNetlist 
reprfesenting -> representing
 2021-05-26 12:31:46 +03:00
Niko Savola bc16c4ad31
Fix missing 'to' typo 
from another cell this cell -> from another cell to this cell
 2021-05-26 10:33:07 +03:00
Matthias Koefferlein 6ad8ec5662 Bugfix: whole edge output for fragmented second input. No way to fix that for the compound ops. Restrict negative output for two-layer checks on first layer for the same reason. 2021-05-26 00:27:13 +02:00
Matthias Koefferlein 19b28982e7 WIP: updated test data (bugfix: bulk does not have layer properties), Fixed Region::count and Region::hier_count (was counting non-polygons too) 2021-05-25 23:08:38 +02:00
Matthias Koefferlein 3789e38ce3 WIP: avoid one more segfault. 2021-05-25 22:45:19 +02:00
Matthias Koefferlein 0d6ce92d6b WIP: fixed a potential segfault 2021-05-25 21:41:27 +02:00
Matthias Koefferlein 0452e91e8c WIP: Some hardening against internal state changes in RecursiveShapeIterator, tests fixed 2021-05-25 21:36:54 +02:00
Matthias Koefferlein 1c8442f485 Fixed #807 - now supporting incremental connect and clear_connections in DRC/LVS 2021-05-24 21:56:57 +02:00
Matthias Koefferlein 58afc47071 WIP: reduced space runtimes (OpenRAM sample) by selective edge processing 2021-05-24 18:27:16 +02:00
Matthias Koefferlein 05b1023fd5 Updated tests. 2021-05-24 16:49:00 +02:00
Matthias Koefferlein 2fc301a0b6 More efficient shape counts on OriginalLayer 2021-05-23 12:21:18 +02:00
Matthias Koefferlein 4bc665cbf3 Mapping deep-mode 'or' (DRC) to 'add' to avoid flat processing. 2021-05-22 22:32:29 +02:00
Matthias Koefferlein 560234cacb Less noisy output with verbose debug mode 2021-05-22 22:29:57 +02:00
Matthias Koefferlein 6cfe14a418 Typo corrected 2021-05-22 22:29:10 +02:00
Niko Savola feb5e7eece
Fix documentation typo in gsiDeclDbCell.cc 2021-05-21 14:35:21 +03:00
Matthias Koefferlein aea8c4d1ad 3-terminal C's and R's for Spice writer too, using different default models for 2- and 3-terminal R and C 2021-05-13 21:13:41 +02:00
Matthias Koefferlein 4eb8f69a22 Spice reader: Support for resistance, capacitance and inductance values within parameters, basic support for 3-terminal resistors, more flexibility in SpiceReaderDelegate. 2021-05-13 20:40:28 +02:00
Matthias Köfferlein 9c5542d3d2
Merge pull request #788 from KLayout/issue-787 
Issue 787 fixed
 2021-05-08 22:26:10 +02:00
Matthias Koefferlein 70864e41af Implemented Edge#cut_point for GSI (was missing) 2021-05-04 21:12:46 +02:00
Matthias Koefferlein 31cc8f32e2 Fixed #787 - the results of const reference return values need to be copied as the holder object may go out of scope 2021-05-02 23:00:38 +02:00
Matthias Koefferlein 1285868546 Skip private-only tests without private data access 2021-05-01 21:36:52 +02:00
Matthias Koefferlein 7c3c631515 Merge branch 'master' into feedback 2021-04-29 23:53:47 +02:00
Matthias Koefferlein 281681fffb Limit hier processor instance/instance and instance/cluster cache depth to 20 entries per cell pair to avoid memory explosion 2021-04-28 22:51:00 +02:00
Matthias Koefferlein 855e8a3518 WIP: some enhancements with the effect of reducing instance interaction caching overhead and improving performance. More memory and cache metrics. 2021-04-27 22:27:22 +02:00
Matthias Koefferlein 2f204eaa21 Some refactoring of the instance-to-instance test in hier processor: gives some performance improvement with less memory for cache. 2021-04-26 23:15:27 +02:00
Matthias Koefferlein 6e52e6f0c6 WIP: introducing memory metrics for netlist/l2n 2021-04-26 22:26:31 +02:00
Matthias Koefferlein 7d8825a9fb Ghost cells are not renamed in blend mode 'rename' 2021-04-24 21:30:03 +02:00
Matthias Köfferlein f8e7e3b6e1
Merge pull request #770 from KLayout/lvs-enhancement 
Lvs enhancement
 2021-04-14 23:24:30 +02:00
Matthias Koefferlein 6ea04d6c27 Small LVS enhancement: reject backtracking branch if it leads to ambiguous name conflicts 2021-04-13 22:57:08 +02:00
Matthias Koefferlein a02c2c8eeb Merge branch 'master' into hierarchical-edges 2021-04-11 22:47:38 +02:00
Matthias Koefferlein 870fd2e0bd Fixed some valgrind issues. 2021-04-08 23:30:47 +02:00
Matthias Koefferlein c4e5310c95 Bugfix: holes and hulls are not neccessarily merged 2021-04-08 00:32:03 +02:00